PMU Events for Cortex-M85

IDs for additional events defined for Cortex-M85. More...

Macros
#define	ARMCM85_PMU_ECC_ERR   0xC000
	Any ECC error.
#define	ARMCM85_PMU_ECC_ERR_MBIT   0xC001
	Any multi-bit ECC error.
#define	ARMCM85_PMU_ECC_ERR_DCACHE   0xC010
	Any ECC error in the data cache.
#define	ARMCM85_PMU_ECC_ERR_ICACHE   0xC011
	Any ECC error in the instruction cache.
#define	ARMCM85_PMU_ECC_ERR_MBIT_DCACHE   0xC012
	Any multi-bit ECC error in the data cache.
#define	ARMCM85_PMU_ECC_ERR_MBIT_ICACHE   0xC013
	Any multi-biy ECC error in the instruction cache.
#define	ARMCM85_PMU_ECC_ERR_DTCM   0xC020
	Any ECC error in the DTCM.
#define	ARMCM85_PMU_ECC_ERR_ITCM   0xC021
	Any ECC error in the ITCM.
#define	ARMCM85_PMU_ECC_ERR_MBIT_DTCM   0xC022
	Any multi-bit ECC error in the DTCM.
#define	ARMCM85_PMU_ECC_ERR_MBIT_ITCM   0xC023
	Any multi-bit ECC error in the ITCM.
#define	ARMCM85_PMU_PF_LINEFILL   0xC100
	A prefetcher starts a line-fill.
#define	ARMCM85_PMU_PF_CANCEL   0xC101
	A prefetcher stops prefetching.
#define	ARMCM85_PMU_PF_DROP_LINEFILL   0xC102
	A linefill triggered by a prefetcher has been dropped because of lack of buffering.
#define	ARMCM85_PMU_NWAMODE_ENTER   0xC200
	No write-allocate mode entry.
#define	ARMCM85_PMU_NWAMODE   0xC201
	Write-allocate store is not allocated into the data cache due to no-write-allocate mode.
#define	ARMCM85_PMU_SAHB_ACCESS   0xC300
	Read or write access on the S-AHB interface to the TCM.
#define	ARMCM85_PMU_PAHB_ACCESS   0xC301
	Read or write access on the P-AHB interface.
#define	ARMCM85_PMU_AXI_WRITE_ACCESS   0xC302
	Any beat access to M-AXI write interface
#define	ARMCM85_PMU_AXI_READ_ACCESS   0xC303
	Any beat access to M-AXI read interface.
#define	ARMCM85_PMU_DOSTIMEOUT_DOUBLE   0xC400
	Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress.
#define	ARMCM85_PMU_DOSTIMEOUT_TRIPLE   0xC401
	Denial of Service timeout has fired three times and blocked the LSU to force forward progress.

Description

IDs for additional events defined for Cortex-M85.

These events are available on a Cortex-M85 device including a PMU.

Macro Definition Documentation

ARMCM85_PMU_AXI_READ_ACCESS

#define ARMCM85_PMU_AXI_READ_ACCESS   0xC303

Any beat access to M-AXI read interface.

ARMCM85_PMU_AXI_WRITE_ACCESS

#define ARMCM85_PMU_AXI_WRITE_ACCESS   0xC302

Any beat access to M-AXI write interface

ARMCM85_PMU_DOSTIMEOUT_DOUBLE

#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE   0xC400

Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress.

ARMCM85_PMU_DOSTIMEOUT_TRIPLE

#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE   0xC401

Denial of Service timeout has fired three times and blocked the LSU to force forward progress.

ARMCM85_PMU_ECC_ERR

#define ARMCM85_PMU_ECC_ERR   0xC000

Any ECC error.

ARMCM85_PMU_ECC_ERR_DCACHE

#define ARMCM85_PMU_ECC_ERR_DCACHE   0xC010

Any ECC error in the data cache.

ARMCM85_PMU_ECC_ERR_DTCM

#define ARMCM85_PMU_ECC_ERR_DTCM   0xC020

Any ECC error in the DTCM.

ARMCM85_PMU_ECC_ERR_ICACHE

#define ARMCM85_PMU_ECC_ERR_ICACHE   0xC011

Any ECC error in the instruction cache.

ARMCM85_PMU_ECC_ERR_ITCM

#define ARMCM85_PMU_ECC_ERR_ITCM   0xC021

Any ECC error in the ITCM.

ARMCM85_PMU_ECC_ERR_MBIT

#define ARMCM85_PMU_ECC_ERR_MBIT   0xC001

Any multi-bit ECC error.

ARMCM85_PMU_ECC_ERR_MBIT_DCACHE

#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE   0xC012

Any multi-bit ECC error in the data cache.

ARMCM85_PMU_ECC_ERR_MBIT_DTCM

#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM   0xC022

Any multi-bit ECC error in the DTCM.

ARMCM85_PMU_ECC_ERR_MBIT_ICACHE

#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE   0xC013

Any multi-biy ECC error in the instruction cache.

ARMCM85_PMU_ECC_ERR_MBIT_ITCM

#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM   0xC023

Any multi-bit ECC error in the ITCM.

ARMCM85_PMU_NWAMODE

#define ARMCM85_PMU_NWAMODE   0xC201

Write-allocate store is not allocated into the data cache due to no-write-allocate mode.

ARMCM85_PMU_NWAMODE_ENTER

#define ARMCM85_PMU_NWAMODE_ENTER   0xC200

No write-allocate mode entry.

ARMCM85_PMU_PAHB_ACCESS

#define ARMCM85_PMU_PAHB_ACCESS   0xC301

Read or write access on the P-AHB interface.

ARMCM85_PMU_PF_CANCEL

#define ARMCM85_PMU_PF_CANCEL   0xC101

A prefetcher stops prefetching.

ARMCM85_PMU_PF_DROP_LINEFILL

#define ARMCM85_PMU_PF_DROP_LINEFILL   0xC102

A linefill triggered by a prefetcher has been dropped because of lack of buffering.

ARMCM85_PMU_PF_LINEFILL

#define ARMCM85_PMU_PF_LINEFILL   0xC100

A prefetcher starts a line-fill.

ARMCM85_PMU_SAHB_ACCESS

#define ARMCM85_PMU_SAHB_ACCESS   0xC300

Read or write access on the S-AHB interface to the TCM.