Bit position and mask macros. More...
Macros | |
| #define | DFSR_CM_Pos 13U | 
| DFSR: CM Position.   | |
| #define | DFSR_CM_Msk (1UL << DFSR_CM_Pos) | 
| DFSR: CM Mask.   | |
| #define | DFSR_Ext_Pos 12U | 
| DFSR: Ext Position.   | |
| #define | DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) | 
| DFSR: Ext Mask.   | |
| #define | DFSR_WnR_Pos 11U | 
| DFSR: WnR Position.   | |
| #define | DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) | 
| DFSR: WnR Mask.   | |
| #define | DFSR_LPAE_Pos 9U | 
| DFSR: LPAE Position.   | |
| #define | DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) | 
| DFSR: LPAE Mask.   | |
| #define | DFSR_FS1_Pos 10U | 
| DFSR: FS1 Position.   | |
| #define | DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) | 
| DFSR: FS1 Mask.   | |
| #define | DFSR_Domain_Pos 4U | 
| DFSR: Domain Position.   | |
| #define | DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) | 
| DFSR: Domain Mask.   | |
| #define | DFSR_FS0_Pos 0U | 
| DFSR: FS0 Position.   | |
| #define | DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) | 
| DFSR: FS0 Mask.   | |
| #define | DFSR_STATUS_Pos 0U | 
| DFSR: STATUS Position.   | |
| #define | DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) | 
| DFSR: STATUS Mask.   | |
Bit position and mask macros.
| #define DFSR_CM_Msk (1UL << DFSR_CM_Pos) | 
DFSR: CM Mask.
| #define DFSR_CM_Pos 13U | 
DFSR: CM Position.
| #define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) | 
DFSR: Domain Mask.
| #define DFSR_Domain_Pos 4U | 
DFSR: Domain Position.
| #define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) | 
DFSR: Ext Mask.
| #define DFSR_Ext_Pos 12U | 
DFSR: Ext Position.
| #define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) | 
DFSR: FS0 Mask.
| #define DFSR_FS0_Pos 0U | 
DFSR: FS0 Position.
| #define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) | 
DFSR: FS1 Mask.
| #define DFSR_FS1_Pos 10U | 
DFSR: FS1 Position.
| #define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) | 
DFSR: LPAE Mask.
| #define DFSR_LPAE_Pos 9U | 
DFSR: LPAE Position.
| #define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) | 
DFSR: STATUS Mask.
| #define DFSR_STATUS_Pos 0U | 
DFSR: STATUS Position.
| #define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) | 
DFSR: WnR Mask.
| #define DFSR_WnR_Pos 11U | 
DFSR: WnR Position.