Bit position and mask macros. More...
Macros | |
#define | IFSR_ExT_Pos 12U |
IFSR: ExT Position. | |
#define | IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) |
IFSR: ExT Mask. | |
#define | IFSR_LPAE_Pos 9U |
IFSR: LPAE Position. | |
#define | IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) |
IFSR: LPAE Mask. | |
#define | IFSR_FS1_Pos 10U |
IFSR: FS1 Position. | |
#define | IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) |
IFSR: FS1 Mask. | |
#define | IFSR_FS0_Pos 0U |
IFSR: FS0 Position. | |
#define | IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) |
IFSR: FS0 Mask. | |
#define | IFSR_STATUS_Pos 0U |
IFSR: STATUS Position. | |
#define | IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) |
IFSR: STATUS Mask. | |
Bit position and mask macros.
#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) |
IFSR: ExT Mask.
#define IFSR_ExT_Pos 12U |
IFSR: ExT Position.
#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) |
IFSR: FS0 Mask.
#define IFSR_FS0_Pos 0U |
IFSR: FS0 Position.
#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) |
IFSR: FS1 Mask.
#define IFSR_FS1_Pos 10U |
IFSR: FS1 Position.
#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) |
IFSR: LPAE Mask.
#define IFSR_LPAE_Pos 9U |
IFSR: LPAE Position.
#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) |
IFSR: STATUS Mask.
#define IFSR_STATUS_Pos 0U |
IFSR: STATUS Position.