CMSIS-Core (Cortex-A)  
CMSIS-Core support for Cortex-A processor-based devices
 
Loading...
Searching...
No Matches
Interrupts and Exceptions

Generic functions to access the Interrupt Controller. More...

Content

 IRQ Mode Bit-Masks
 Configure interrupt line mode.
 
 IRQ Priority Bit-Masks
 Definitions used by interrupt priority functions.
 

Enumerations

enum  IRQn_Type {
  SGI0_IRQn = 0 ,
  SGI1_IRQn = 1 ,
  SGI2_IRQn = 2 ,
  SGI3_IRQn = 3 ,
  SGI4_IRQn = 4 ,
  SGI5_IRQn = 5 ,
  SGI6_IRQn = 6 ,
  SGI7_IRQn = 7 ,
  SGI8_IRQn = 8 ,
  SGI9_IRQn = 9 ,
  SGI10_IRQn = 10 ,
  SGI11_IRQn = 11 ,
  SGI12_IRQn = 12 ,
  SGI13_IRQn = 13 ,
  SGI14_IRQn = 14 ,
  SGI15_IRQn = 15 ,
  VirtualMaintenanceInterrupt_IRQn = 25 ,
  HypervisorTimer_IRQn = 26 ,
  VirtualTimer_IRQn = 27 ,
  Legacy_nFIQ_IRQn = 28 ,
  SecurePhyTimer_IRQn = 29 ,
  NonSecurePhyTimer_IRQn = 30 ,
  Legacy_nIRQ_IRQn = 31
}
 Definition of IRQn numbers. More...
 

Functions

int32_t IRQ_Initialize (void)
 Initialize interrupt controller.
 
int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler)
 Register interrupt handler.
 
IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn)
 Get the registered interrupt handler.
 
int32_t IRQ_Enable (IRQn_ID_t irqn)
 Enable interrupt.
 
int32_t IRQ_Disable (IRQn_ID_t irqn)
 Disable interrupt.
 
uint32_t IRQ_GetEnableState (IRQn_ID_t irqn)
 Get interrupt enable state.
 
int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode)
 Configure interrupt request mode.
 
uint32_t IRQ_GetMode (IRQn_ID_t irqn)
 Get interrupt mode configuration.
 
IRQn_ID_t IRQ_GetActiveIRQ (void)
 Get ID number of current interrupt request (IRQ).
 
IRQn_ID_t IRQ_GetActiveFIQ (void)
 Get ID number of current fast interrupt request (FIQ).
 
int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn)
 Signal end of interrupt processing.
 
int32_t IRQ_SetPending (IRQn_ID_t irqn)
 Set interrupt pending flag.
 
uint32_t IRQ_GetPending (IRQn_ID_t irqn)
 Get interrupt pending flag.
 
int32_t IRQ_ClearPending (IRQn_ID_t irqn)
 Clear interrupt pending flag.
 
int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority)
 Set interrupt priority value.
 
uint32_t IRQ_GetPriority (IRQn_ID_t irqn)
 Get interrupt priority.
 
int32_t IRQ_SetPriorityMask (uint32_t priority)
 Set priority masking threshold.
 
uint32_t IRQ_GetPriorityMask (void)
 Get priority masking threshold.
 
int32_t IRQ_SetPriorityGroupBits (uint32_t bits)
 Set priority grouping field split point.
 
uint32_t IRQ_GetPriorityGroupBits (void)
 Get priority grouping field split point.
 

Description

Generic functions to access the Interrupt Controller.

This section describes the device agnostic interrupt API viable for a wide range of specific interrupt controllers. The IRQ Controller API allows interrupt dependend applications to be easily portable across a wide range of controllers.

Note
The default implementation for Arm GIC (Generic Interrupt Controller) can be found in irq_ctrl_gic.c. It uses weak functions thus it can easily be overwritten by an alternative user implementation if needed.

The Armv7-A architecture defines a common set of first level exceptions, see table below.

Exception CMSIS Handler Offset Description
Reset Reset_Handler 0x0000 First instruction executed after reset.
Undefined Instruction (Undef) Undef_Handler 0x0004 Signals usage of an illegal instructions.
Supervisor Call (SVC) SVC_Handler 0x0008 Issued by software using SVC instruction.
Prefetch Abort (PAbt) PAbt_Handler 0x000C Signals a memory abort on istruction fetch.
Data Abort (DAbt) DAbt_Handler 0x0010 Signals a memory abort on data read or write.
Hyp Trap (NOP) 0x0014 Hypervisor instruction trap, only available with Virtualization Extensions.
IRQ interrupt IRQ_Handler 0x0018 Interrupt Request (typically from Interrupt Controller)
FIQ interrupt FIQ_Handler 0x001C Fast Interrupt Request (typically from Interrupt Controller)

By default those handlers are defined as weak empty functions by the device specific startup code. Software and peripheral interrupts are all handled by one of the both central interrupt handlers (IRQ and FIQ). These needs to be implemented application specific. If an RTOS is used the interrupt handlers are typically provided by the RTOS, e.g. when using CMSIS-RTX.

The interrupts available depends on the actual device in use. According to CMSIS specification the interrupts are defined in IRQn_Type in Device Header File <Device.h>. Using the generic IRQ API one can easily enable and disable interrupts, set up priorities, modes and preemption rules, and register interrupt callbacks.

Example:

void SGI0_Handler() {
/*
* Handle Interrupt
*/
}
void main() {
/* Initialize the Interrupt Controller */
/* Register the user defined handler function */
/* Set the priority considering the priority grouping */
const uint32_t subprio = IRQ_GetPriorityGroupBits();
/* Set interrupt mode to falling edge */
/* Trigger interrupt */
}
int32_t IRQ_Initialize(void)
Initialize interrupt controller.
uint32_t IRQ_GetPriorityGroupBits(void)
Get priority grouping field split point.
int32_t IRQ_Enable(IRQn_ID_t irqn)
Enable interrupt.
int32_t IRQ_Disable(IRQn_ID_t irqn)
Disable interrupt.
int32_t IRQ_SetPending(IRQn_ID_t irqn)
Set interrupt pending flag.
int32_t IRQ_SetPriority(IRQn_ID_t irqn, uint32_t priority)
Set interrupt priority value.
int32_t IRQ_ClearPending(IRQn_ID_t irqn)
Clear interrupt pending flag.
int32_t IRQ_SetMode(IRQn_ID_t irqn, uint32_t mode)
Configure interrupt request mode.
int32_t IRQ_SetHandler(IRQn_ID_t irqn, IRQHandler_t handler)
Register interrupt handler.
@ SGI0_IRQn
Software Generated Interrupt 0.
Definition: ref_irq_ctrl.txt:82
#define IRQ_MODE_TRIG_EDGE_FALLING
Trigger: falling edge triggered interrupt.
#define IRQ_MODE_TRIG_EDGE
Trigger: edge triggered interrupt.
#define IRQ_MODE_TYPE_IRQ
Type: interrupt source triggers CPU IRQ line.
#define IRQ_MODE_CPU_0
CPU: interrupt targets CPU 0.
int32_t IRQn_ID_t
Interrupt ID number data type.
Definition: irq_ctrl.h:43

Enumeration Type Documentation

◆ IRQn_Type

enum IRQn_Type

Definition of IRQn numbers.

The core exception enumeration names for IRQn values are defined in the Device Header File <Device.h>.

The table below describes the core exception names in Cortex-A core.

Enumerator
SGI0_IRQn 

Software Generated Interrupt 0.

SGI1_IRQn 

Software Generated Interrupt 1.

SGI2_IRQn 

Software Generated Interrupt 2.

SGI3_IRQn 

Software Generated Interrupt 3.

SGI4_IRQn 

Software Generated Interrupt 4.

SGI5_IRQn 

Software Generated Interrupt 5.

SGI6_IRQn 

Software Generated Interrupt 6.

SGI7_IRQn 

Software Generated Interrupt 7.

SGI8_IRQn 

Software Generated Interrupt 8.

SGI9_IRQn 

Software Generated Interrupt 9.

SGI10_IRQn 

Software Generated Interrupt 10.

SGI11_IRQn 

Software Generated Interrupt 11.

SGI12_IRQn 

Software Generated Interrupt 12.

SGI13_IRQn 

Software Generated Interrupt 13.

SGI14_IRQn 

Software Generated Interrupt 14.

SGI15_IRQn 

Software Generated Interrupt 15.

VirtualMaintenanceInterrupt_IRQn 

Virtual Maintenance Interrupt.

HypervisorTimer_IRQn 

Hypervisor Timer Interrupt.

VirtualTimer_IRQn 

Virtual Timer Interrupt.

Legacy_nFIQ_IRQn 

Legacy nFIQ Interrupt.

SecurePhyTimer_IRQn 

Secure Physical Timer Interrupt.

NonSecurePhyTimer_IRQn 

Non-Secure Physical Timer Interrupt.

Legacy_nIRQ_IRQn 

Legacy nIRQ Interrupt.

Function Documentation

◆ IRQ_ClearPending()

int32_t IRQ_ClearPending ( IRQn_ID_t  irqn)

Clear interrupt pending flag.

Parameters
[in]irqninterrupt ID number
Returns
0 on success, -1 on error.

This function clears the pending status of the interrupt identified by the irqn parameter.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 16) && (irqn < IRQ_GIC_LINE_COUNT)) {
status = 0;
} else {
status = -1;
}
return (status);
}
__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
Clears the given interrupt from being pending using GIC's ICPENDR register.
Definition: core_ca.h:1614
IRQn_Type
Definition of IRQn numbers.
Definition: ref_irq_ctrl.txt:79

◆ IRQ_Disable()

int32_t IRQ_Disable ( IRQn_ID_t  irqn)

Disable interrupt.

Parameters
[in]irqninterrupt ID number
Returns
0 on success, -1 on error.

This function disables forwarding of the corresponding interrupt to the CPU.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_Disable (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
status = 0;
} else {
status = -1;
}
return (status);
}
__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
Disables the given interrupt using GIC's ICENABLER register.
Definition: core_ca.h:1568

◆ IRQ_Enable()

int32_t IRQ_Enable ( IRQn_ID_t  irqn)

Enable interrupt.

Parameters
[in]irqninterrupt ID number
Returns
0 on success, -1 on error.

This function enables forwarding of the corresponding interrupt to the CPU.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_Enable (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
status = 0;
} else {
status = -1;
}
return (status);
}
__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
Enables the given interrupt using GIC's ISENABLER register.
Definition: core_ca.h:1551

◆ IRQ_EndOfInterrupt()

int32_t IRQ_EndOfInterrupt ( IRQn_ID_t  irqn)

Signal end of interrupt processing.

Parameters
[in]irqninterrupt ID number
Returns
0 on success, -1 on error.

This function informs the interrupt controller that the interrupt service routine processing of the currently active interrupt request is completed.

The parameter irqn should specify the value previously returned by the IRQ_GetActiveIRQ or IRQ_GetActiveFIQ functions.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
if (irqn == 0) {
IRQ_ID0 = 0U;
}
status = 0;
} else {
status = -1;
}
return (status);
}
__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
Writes the given interrupt number to the CPU's EOIR register.
Definition: core_ca.h:1543
int32_t IRQ_EndOfInterrupt(IRQn_ID_t irqn)
Signal end of interrupt processing.

◆ IRQ_GetActiveFIQ()

IRQn_ID_t IRQ_GetActiveFIQ ( void  )

Get ID number of current fast interrupt request (FIQ).

Returns
interrupt ID number.

This function retrieves the interrupt ID number of current FIQ source and acknowledges the interrupt.

For Arm GIC the default implementation looks like the following example:

// FIQ is not supported, return invalid ID
return ((IRQn_ID_t)-1);
}
IRQn_ID_t IRQ_GetActiveFIQ(void)
Get ID number of current fast interrupt request (FIQ).

◆ IRQ_GetActiveIRQ()

IRQn_ID_t IRQ_GetActiveIRQ ( void  )

Get ID number of current interrupt request (IRQ).

Returns
interrupt ID number.

This function retrieves the interrupt ID number of current IRQ source and acknowledges the interrupt.

For Arm GIC the default implementation looks like the following example:

IRQn_ID_t irqn;
return (irqn);
}
__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
Read the CPU's IAR register.
Definition: core_ca.h:1535
IRQn_ID_t IRQ_GetActiveIRQ(void)
Get ID number of current interrupt request (IRQ).

◆ IRQ_GetEnableState()

uint32_t IRQ_GetEnableState ( IRQn_ID_t  irqn)

Get interrupt enable state.

Parameters
[in]irqninterrupt ID number
Returns
0 - interrupt is disabled, 1 - interrupt is enabled.

This function retrieves the interrupt enable status of the interrupt identified by the irqn parameter.

Interrupt enable status can be either disabled (0) or enabled (1). Disabled status is returned for interrupts which cannot be identified by irqn.

For Arm GIC the default implementation looks like the following example:

uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
uint32_t enable;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
} else {
enable = 0U;
}
return (enable);
}
__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn)
Get interrupt enable status using GIC's ISENABLER register.
Definition: core_ca.h:1560
uint32_t IRQ_GetEnableState(IRQn_ID_t irqn)
Get interrupt enable state.

◆ IRQ_GetHandler()

IRQHandler_t IRQ_GetHandler ( IRQn_ID_t  irqn)

Get the registered interrupt handler.

Parameters
[in]irqninterrupt ID number
Returns
registered interrupt handler function address.

This function retrieves address of the interrupt handler callback function corresponding to the specified interrupt ID number.

For Arm GIC the default implementation looks like the following example:

IRQHandler h;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
h = IRQTable[irqn];
} else {
h = (IRQHandler_t)0;
}
return (h);
}
IRQHandler_t IRQ_GetHandler(IRQn_ID_t irqn)
Get the registered interrupt handler.
void(* IRQHandler_t)(void)
Interrupt handler data type.
Definition: irq_ctrl.h:37

◆ IRQ_GetMode()

uint32_t IRQ_GetMode ( IRQn_ID_t  irqn)

Get interrupt mode configuration.

Parameters
[in]irqninterrupt ID number
Returns
current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.

This function retrieves interrupt mode configuration of the interrupt identified by the irqn parameter. IRQ_MODE_ERROR is returned for interrupts which cannot be identified by irqn.

For Arm GIC the default implementation looks like the following example:

uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
uint32_t mode;
uint32_t val;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
// Get trigger mode
if ((val & 2U) != 0U) {
// Corresponding interrupt is edge triggered
} else {
// Corresponding interrupt is level triggered
}
// Get interrupt CPU targets
} else {
}
return (mode);
}
__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn)
Get the interrupt configuration from the GIC's ICFGR register.
Definition: core_ca.h:1646
__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
Read the GIC's ITARGETSR register.
Definition: core_ca.h:1513
uint32_t IRQ_GetMode(IRQn_ID_t irqn)
Get interrupt mode configuration.
#define IRQ_MODE_ERROR
Bit indicating mode value error.
#define IRQ_MODE_TRIG_LEVEL
Trigger: level triggered interrupt.
#define IRQ_MODE_CPU_Pos
Definition: irq_ctrl.h:67

◆ IRQ_GetPending()

uint32_t IRQ_GetPending ( IRQn_ID_t  irqn)

Get interrupt pending flag.

Parameters
[in]irqninterrupt ID number
Returns
0 - interrupt is not pending, 1 - interrupt is pending.

This function retrieves the pending status of the interrupt identified by the irqn parameter.

Interrupt pending status can be either not pending (0) or pending (1). Not pending status is returned for interrupts which cannot be identified by irqn.

For Arm GIC the default implementation looks like the following example:

uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
uint32_t pending;
if ((irqn >= 16) && (irqn < IRQ_GIC_LINE_COUNT)) {
pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
} else {
pending = 0U;
}
return (pending & 1U);
}
__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn)
Get interrupt pending status from GIC's ISPENDR register.
Definition: core_ca.h:1577
uint32_t IRQ_GetPending(IRQn_ID_t irqn)
Get interrupt pending flag.

◆ IRQ_GetPriority()

uint32_t IRQ_GetPriority ( IRQn_ID_t  irqn)

Get interrupt priority.

Parameters
[in]irqninterrupt ID number
Returns
current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.

This function retrieves the priority of the interrupt identified by the irqn parameter.

The valid priority value can be from zero (0) to the value of IRQ_PRIORITY_Msk. IRQ_PRIORITY_ERROR bit is set in returned value for interrupts which cannot be identified by irqn.

For Arm GIC the default implementation looks like the following example:

uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
uint32_t priority;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
priority = GIC_GetPriority ((IRQn_Type)irqn);
} else {
priority = IRQ_PRIORITY_ERROR;
}
return (priority);
}
__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
Read the current interrupt priority from GIC's IPRIORITYR register.
Definition: core_ca.h:1664
uint32_t IRQ_GetPriority(IRQn_ID_t irqn)
Get interrupt priority.
#define IRQ_PRIORITY_ERROR
Bit indicating priority value error.

◆ IRQ_GetPriorityGroupBits()

uint32_t IRQ_GetPriorityGroupBits ( void  )

Get priority grouping field split point.

Returns
current number of MSB bits included in the group priority field comparison with optional IRQ_PRIORITY_ERROR bit set.

This function retrieves the number of MSB bits used to determine whether a pending interrupt has sufficient priority to preempt a currently active interrupt.

IRQ_PRIORITY_ERROR value is returned when priority grouping is not supported.

For Arm GIC the default implementation looks like the following example:

uint32_t IRQ_GetPriorityGroupBits (void) {
uint32_t bp;
bp = GIC_GetBinaryPoint() & 0x07U;
return (7U - bp);
}
__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
Read the current group priority and subpriority split point from CPU's BPR register.
Definition: core_ca.h:1696

◆ IRQ_GetPriorityMask()

uint32_t IRQ_GetPriorityMask ( void  )

Get priority masking threshold.

Returns
current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.

This function retrieves the priority masking threshold for the current processor.

IRQ_PRIORITY_ERROR value is returned if priority masking is not supported.

For Arm GIC the default implementation looks like the following example:

uint32_t IRQ_GetPriorityMask (void) {
}
__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
Read the current interrupt priority mask from CPU's PMR register.
Definition: core_ca.h:1680
uint32_t IRQ_GetPriorityMask(void)
Get priority masking threshold.

◆ IRQ_Initialize()

int32_t IRQ_Initialize ( void  )

Initialize interrupt controller.

Returns
0 on success, -1 on error.

This function initializes interrupt controller.

It disables all interrupt sources, clears all pending interrupts, sets interrupt priorities to highest priority and configures priority mask to lowest priority. IRQ and FIQ signal lines should be enabled and all interrupt handlers should be set to NULL.

For Arm GIC the default implementation looks like the following example:

#ifndef IRQ_GIC_LINE_COUNT
#define IRQ_GIC_LINE_COUNT (1020U)
#endif
static IRQHandler IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
int32_t IRQ_Initialize (void) {
uint32_t i;
for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
IRQTable[i] = (IRQHandler)NULL;
}
return (0);
}
__STATIC_INLINE void GIC_Enable(void)
Initialize and enable the GIC.
Definition: core_ca.h:1845

◆ IRQ_SetHandler()

int32_t IRQ_SetHandler ( IRQn_ID_t  irqn,
IRQHandler_t  handler 
)

Register interrupt handler.

Parameters
[in]irqninterrupt ID number
[in]handlerinterrupt handler function address
Returns
0 on success, -1 on error.

This function registers address of the interrupt handler callback function corresponding to the specified interrupt ID number.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
IRQTable[irqn] = handler;
status = 0;
} else {
status = -1;
}
return (status);
}

◆ IRQ_SetMode()

int32_t IRQ_SetMode ( IRQn_ID_t  irqn,
uint32_t  mode 
)

Configure interrupt request mode.

Parameters
[in]irqninterrupt ID number
[in]modemode configuration
Returns
0 on success, -1 on error.

This function configures the interrupt triggering mode, type, secure access and target CPUs of the interrupt (see IRQ Mode Bit-Masks) identified by the irqn parameter.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
int32_t status;
uint32_t val;
uint8_t cfg;
uint8_t secure;
uint8_t cpu;
status = 0;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
// Check triggering mode
val = (mode & IRQ_MODE_TRIG_Msk);
if (val == IRQ_MODE_TRIG_LEVEL) {
cfg = 0x00U;
} else if (val == IRQ_MODE_TRIG_EDGE) {
cfg = 0x02U;
} else {
status = -1;
}
// Check interrupt type
val = mode & IRQ_MODE_TYPE_Msk;
if (val != IRQ_MODE_TYPE_IRQ) {
status = -1;
}
// Check interrupt domain
val = mode & IRQ_MODE_DOMAIN_Msk;
secure = 0;
} else {
// Check security extensions support
val = GIC_DistributorInfo() & (1UL << 10U);
if (val != 0U) {
// Security extensions are supported
secure = 1;
} else {
status = -1;
}
}
// Check interrupt CPU targets
val = mode & IRQ_MODE_CPU_Msk;
if (val == IRQ_MODE_CPU_ALL) {
cpu = 0xFF;
} else {
cpu = val >> IRQ_MODE_CPU_Pos;
}
// Apply configuration if no mode error
if (status == 0) {
GIC_SetTarget ((IRQn_Type)irqn, cpu);
if (secure != 0U) {
GIC_SetGroup ((IRQn_Type)irqn, secure);
}
}
}
return (status);
}
__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config)
Sets the interrupt configuration using GIC's ICFGR register.
Definition: core_ca.h:1629
__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group)
Set the interrupt group from the GIC's IGROUPR register.
Definition: core_ca.h:1745
__STATIC_INLINE uint32_t GIC_DistributorInfo(void)
Read the GIC's TYPER register.
Definition: core_ca.h:1486
__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
Sets the GIC's ITARGETSR register for the given interrupt.
Definition: core_ca.h:1503
#define IRQ_MODE_DOMAIN_NONSECURE
Domain: interrupt is targeting non-secure domain.
#define IRQ_MODE_CPU_ALL
CPU: interrupt targets all CPUs.
#define IRQ_MODE_TRIG_Msk
Definition: irq_ctrl.h:48
#define IRQ_MODE_TYPE_Msk
Definition: irq_ctrl.h:58
#define IRQ_MODE_CPU_Msk
Definition: irq_ctrl.h:68
#define IRQ_MODE_DOMAIN_Msk
Definition: irq_ctrl.h:63

◆ IRQ_SetPending()

int32_t IRQ_SetPending ( IRQn_ID_t  irqn)

Set interrupt pending flag.

Parameters
[in]irqninterrupt ID number
Returns
0 on success, -1 on error.

This function sets the pending status of the interrupt identified by the irqn parameter.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_SetPending (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
status = 0;
} else {
status = -1;
}
return (status);
}
__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
Sets the given interrupt as pending using GIC's ISPENDR register.
Definition: core_ca.h:1600

◆ IRQ_SetPriority()

int32_t IRQ_SetPriority ( IRQn_ID_t  irqn,
uint32_t  priority 
)

Set interrupt priority value.

Parameters
[in]irqninterrupt ID number
[in]priorityinterrupt priority value
Returns
0 on success, -1 on error.

This function sets the priority of the interrupt identified by the irqn parameter.

Higher priority numbers have lower priority. The highest interrupt priority has priority value 0, while the lowest value depends on the number of implemented priority levels.

The number of implemented priority bits can be determined by setting value IRQ_PRIORITY_Msk to arbitrary irqn and by retrieving the actual stored value with IRQ_GetPriority function.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
GIC_SetPriority ((IRQn_Type)irqn, priority);
status = 0;
} else {
status = -1;
}
return (status);
}
__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set the priority for the given interrupt in the GIC's IPRIORITYR register.
Definition: core_ca.h:1655

◆ IRQ_SetPriorityGroupBits()

int32_t IRQ_SetPriorityGroupBits ( uint32_t  bits)

Set priority grouping field split point.

Parameters
[in]bitsnumber of MSB bits included in the group priority field comparison
Returns
0 on success, -1 on error.

This function sets the number of MSB priority bits used to determine whether a pending interrupt has sufficient priority to preempt a currently active interrupt.

The number of implemented group priority bits can be determined by setting value IRQ_PRIORITY_Msk and by retrieving the actual stored value with IRQ_GetPriorityGroupBits function. Function returns error status -1 if priority grouping is not supported.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
int32_t status;
if (bits == IRQ_PRIORITY_Msk) {
bits = 7U;
}
if (bits < 8U) {
GIC_SetBinaryPoint (7U - bits);
status = 0;
} else {
status = -1;
}
return (status);
}
__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
Configures the group priority and subpriority split point using CPU's BPR register.
Definition: core_ca.h:1688
int32_t IRQ_SetPriorityGroupBits(uint32_t bits)
Set priority grouping field split point.
#define IRQ_PRIORITY_Msk
Interrupt priority value bit-mask.

◆ IRQ_SetPriorityMask()

int32_t IRQ_SetPriorityMask ( uint32_t  priority)

Set priority masking threshold.

Parameters
[in]prioritypriority masking threshold value
Returns
0 on success, -1 on error.

This function sets the priority masking threshold for the current processor.

It ensures that only interrupts with a higher priority than priority threshold value are signaled to the target processor. Function returns error status -1 if priority masking is not supported.

For Arm GIC the default implementation looks like the following example:

IRQ_SetPriorityMask (uint32_t priority) {
return (0);
}
__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
Set the interrupt priority mask using CPU's PMR register.
Definition: core_ca.h:1672
int32_t IRQ_SetPriorityMask(uint32_t priority)
Set priority masking threshold.