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| #define | ARM_SPI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */ |
| |
| #define | _ARM_Driver_SPI_(n) Driver_SPI##n |
| |
| #define | ARM_Driver_SPI_(n) _ARM_Driver_SPI_(n) |
| |
| #define | ARM_SPI_CONTROL_Pos 0 |
| |
| #define | ARM_SPI_CONTROL_Msk (0xFFUL << ARM_SPI_CONTROL_Pos) |
| |
| #define | ARM_SPI_MODE_INACTIVE (0x00UL << ARM_SPI_CONTROL_Pos) |
| | SPI Inactive.
|
| |
| #define | ARM_SPI_MODE_MASTER (0x01UL << ARM_SPI_CONTROL_Pos) |
| | SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps.
|
| |
| #define | ARM_SPI_MODE_SLAVE (0x02UL << ARM_SPI_CONTROL_Pos) |
| | SPI Slave (Output on MISO, Input on MOSI)
|
| |
| #define | ARM_SPI_MODE_MASTER_SIMPLEX (0x03UL << ARM_SPI_CONTROL_Pos) |
| | SPI Master (Output/Input on MOSI); arg = Bus Speed in bps.
|
| |
| #define | ARM_SPI_MODE_SLAVE_SIMPLEX (0x04UL << ARM_SPI_CONTROL_Pos) |
| | SPI Slave (Output/Input on MISO)
|
| |
| #define | ARM_SPI_FRAME_FORMAT_Pos 8 |
| |
| #define | ARM_SPI_FRAME_FORMAT_Msk (7UL << ARM_SPI_FRAME_FORMAT_Pos) |
| |
| #define | ARM_SPI_CPOL0_CPHA0 (0UL << ARM_SPI_FRAME_FORMAT_Pos) |
| | Clock Polarity 0, Clock Phase 0 (default)
|
| |
| #define | ARM_SPI_CPOL0_CPHA1 (1UL << ARM_SPI_FRAME_FORMAT_Pos) |
| | Clock Polarity 0, Clock Phase 1.
|
| |
| #define | ARM_SPI_CPOL1_CPHA0 (2UL << ARM_SPI_FRAME_FORMAT_Pos) |
| | Clock Polarity 1, Clock Phase 0.
|
| |
| #define | ARM_SPI_CPOL1_CPHA1 (3UL << ARM_SPI_FRAME_FORMAT_Pos) |
| | Clock Polarity 1, Clock Phase 1.
|
| |
| #define | ARM_SPI_TI_SSI (4UL << ARM_SPI_FRAME_FORMAT_Pos) |
| | Texas Instruments Frame Format.
|
| |
| #define | ARM_SPI_MICROWIRE (5UL << ARM_SPI_FRAME_FORMAT_Pos) |
| | National Semiconductor Microwire Frame Format.
|
| |
| #define | ARM_SPI_DATA_BITS_Pos 12 |
| |
| #define | ARM_SPI_DATA_BITS_Msk (0x3FUL << ARM_SPI_DATA_BITS_Pos) |
| |
| #define | ARM_SPI_DATA_BITS(n) (((n) & 0x3FUL) << ARM_SPI_DATA_BITS_Pos) |
| | Number of Data bits.
|
| |
| #define | ARM_SPI_BIT_ORDER_Pos 18 |
| |
| #define | ARM_SPI_BIT_ORDER_Msk (1UL << ARM_SPI_BIT_ORDER_Pos) |
| |
| #define | ARM_SPI_MSB_LSB (0UL << ARM_SPI_BIT_ORDER_Pos) |
| | SPI Bit order from MSB to LSB (default)
|
| |
| #define | ARM_SPI_LSB_MSB (1UL << ARM_SPI_BIT_ORDER_Pos) |
| | SPI Bit order from LSB to MSB.
|
| |
| #define | ARM_SPI_SS_MASTER_MODE_Pos 19 |
| |
| #define | ARM_SPI_SS_MASTER_MODE_Msk (3UL << ARM_SPI_SS_MASTER_MODE_Pos) |
| |
| #define | ARM_SPI_SS_MASTER_UNUSED (0UL << ARM_SPI_SS_MASTER_MODE_Pos) |
| | SPI Slave Select when Master: Not used (default)
|
| |
| #define | ARM_SPI_SS_MASTER_SW (1UL << ARM_SPI_SS_MASTER_MODE_Pos) |
| | SPI Slave Select when Master: Software controlled.
|
| |
| #define | ARM_SPI_SS_MASTER_HW_OUTPUT (2UL << ARM_SPI_SS_MASTER_MODE_Pos) |
| | SPI Slave Select when Master: Hardware controlled Output.
|
| |
| #define | ARM_SPI_SS_MASTER_HW_INPUT (3UL << ARM_SPI_SS_MASTER_MODE_Pos) |
| | SPI Slave Select when Master: Hardware monitored Input.
|
| |
| #define | ARM_SPI_SS_SLAVE_MODE_Pos 21 |
| |
| #define | ARM_SPI_SS_SLAVE_MODE_Msk (1UL << ARM_SPI_SS_SLAVE_MODE_Pos) |
| |
| #define | ARM_SPI_SS_SLAVE_HW (0UL << ARM_SPI_SS_SLAVE_MODE_Pos) |
| | SPI Slave Select when Slave: Hardware monitored (default)
|
| |
| #define | ARM_SPI_SS_SLAVE_SW (1UL << ARM_SPI_SS_SLAVE_MODE_Pos) |
| | SPI Slave Select when Slave: Software controlled.
|
| |
| #define | ARM_SPI_SET_BUS_SPEED (0x10UL << ARM_SPI_CONTROL_Pos) |
| | Set Bus Speed in bps; arg = value.
|
| |
| #define | ARM_SPI_GET_BUS_SPEED (0x11UL << ARM_SPI_CONTROL_Pos) |
| | Get Bus Speed in bps.
|
| |
| #define | ARM_SPI_SET_DEFAULT_TX_VALUE (0x12UL << ARM_SPI_CONTROL_Pos) |
| | Set default Transmit value; arg = value.
|
| |
| #define | ARM_SPI_CONTROL_SS (0x13UL << ARM_SPI_CONTROL_Pos) |
| | Control Slave Select; arg: 0=inactive, 1=active.
|
| |
| #define | ARM_SPI_ABORT_TRANSFER (0x14UL << ARM_SPI_CONTROL_Pos) |
| | Abort current data transfer.
|
| |
| #define | ARM_SPI_SS_INACTIVE 0UL |
| | SPI Slave Select Signal Inactive.
|
| |
| #define | ARM_SPI_SS_ACTIVE 1UL |
| | SPI Slave Select Signal Active.
|
| |
| #define | ARM_SPI_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) |
| | Specified Mode not supported.
|
| |
| #define | ARM_SPI_ERROR_FRAME_FORMAT (ARM_DRIVER_ERROR_SPECIFIC - 2) |
| | Specified Frame Format not supported.
|
| |
| #define | ARM_SPI_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) |
| | Specified number of Data bits not supported.
|
| |
| #define | ARM_SPI_ERROR_BIT_ORDER (ARM_DRIVER_ERROR_SPECIFIC - 4) |
| | Specified Bit order not supported.
|
| |
| #define | ARM_SPI_ERROR_SS_MODE (ARM_DRIVER_ERROR_SPECIFIC - 5) |
| | Specified Slave Select Mode not supported.
|
| |
| #define | ARM_SPI_EVENT_TRANSFER_COMPLETE (1UL << 0) |
| | Data Transfer completed.
|
| |
| #define | ARM_SPI_EVENT_DATA_LOST (1UL << 1) |
| | Data lost: Receive overflow / Transmit underflow.
|
| |
| #define | ARM_SPI_EVENT_MODE_FAULT (1UL << 2) |
| | Master Mode Fault (SS deactivated when Master)
|
| |
