CMSIS-Core (Cortex-M)  Version 5.4.0
CMSIS-Core support for Cortex-M processor-based devices
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PMU Events for Cortex-M55

IDs for additional events defined for Cortex-M55. More...

Macros

#define ARMCM55_PMU_ECC_ERR   0xC000
 Any ECC error. More...
 
#define ARMCM55_PMU_ECC_ERR_FATAL   0xC001
 Any fatal ECC error. More...
 
#define ARMCM55_PMU_ECC_ERR_DCACHE   0xC010
 Any ECC error in the data cache. More...
 
#define ARMCM55_PMU_ECC_ERR_ICACHE   0xC011
 Any ECC error in the instruction cache. More...
 
#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE   0xC012
 Any fatal ECC error in the data cache. More...
 
#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE   0xC013
 Any fatal ECC error in the instruction cache. More...
 
#define ARMCM55_PMU_ECC_ERR_DTCM   0xC020
 Any ECC error in the DTCM. More...
 
#define ARMCM55_PMU_ECC_ERR_ITCM   0xC021
 Any ECC error in the ITCM. More...
 
#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM   0xC022
 Any fatal ECC error in the DTCM. More...
 
#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM   0xC023
 Any fatal ECC error in the ITCM. More...
 
#define ARMCM55_PMU_PF_LINEFILL   0xC100
 A prefetcher starts a line-fill. More...
 
#define ARMCM55_PMU_PF_CANCEL   0xC101
 A prefetcher stops prefetching. More...
 
#define ARMCM55_PMU_PF_DROP_LINEFILL   0xC102
 A linefill triggered by a prefetcher has been dropped because of lack of buffering. More...
 
#define ARMCM55_PMU_NWAMODE_ENTER   0xC200
 No write-allocate mode entry. More...
 
#define ARMCM55_PMU_NWAMODE   0xC201
 Write-allocate store is not allocated into the data cache due to no-write-allocate mode. More...
 
#define ARMCM55_PMU_SAHB_ACCESS   0xC300
 Read or write access on the S-AHB interface to the TCM. More...
 
#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE   0xC400
 Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress. More...
 
#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE   0xC401
 Denial of Service timeout has fired three times and blocked the LSU to force forward progress. More...
 

Description

IDs for additional events defined for Cortex-M55.

These events are available on a Cortex-M55 device including a PMU.

Macro Definition Documentation

#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE   0xC400

Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress.

#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE   0xC401

Denial of Service timeout has fired three times and blocked the LSU to force forward progress.

#define ARMCM55_PMU_ECC_ERR   0xC000

Any ECC error.

#define ARMCM55_PMU_ECC_ERR_DCACHE   0xC010

Any ECC error in the data cache.

#define ARMCM55_PMU_ECC_ERR_DTCM   0xC020

Any ECC error in the DTCM.

#define ARMCM55_PMU_ECC_ERR_FATAL   0xC001

Any fatal ECC error.

#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE   0xC012

Any fatal ECC error in the data cache.

#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM   0xC022

Any fatal ECC error in the DTCM.

#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE   0xC013

Any fatal ECC error in the instruction cache.

#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM   0xC023

Any fatal ECC error in the ITCM.

#define ARMCM55_PMU_ECC_ERR_ICACHE   0xC011

Any ECC error in the instruction cache.

#define ARMCM55_PMU_ECC_ERR_ITCM   0xC021

Any ECC error in the ITCM.

#define ARMCM55_PMU_NWAMODE   0xC201

Write-allocate store is not allocated into the data cache due to no-write-allocate mode.

#define ARMCM55_PMU_NWAMODE_ENTER   0xC200

No write-allocate mode entry.

#define ARMCM55_PMU_PF_CANCEL   0xC101

A prefetcher stops prefetching.

#define ARMCM55_PMU_PF_DROP_LINEFILL   0xC102

A linefill triggered by a prefetcher has been dropped because of lack of buffering.

#define ARMCM55_PMU_PF_LINEFILL   0xC100

A prefetcher starts a line-fill.

#define ARMCM55_PMU_SAHB_ACCESS   0xC300

Read or write access on the S-AHB interface to the TCM.