MPU_Type Struct Reference

Structure type to access the Memory Protection Unit (MPU). More...

Data Fields
__IM uint32_t	TYPE
	Offset: 0x000 (R/ ) MPU Type Register. More...
__IOM uint32_t	CTRL
	Offset: 0x004 (R/W) MPU Control Register. More...
__IOM uint32_t	RNR
	Offset: 0x008 (R/W) MPU Region RNRber Register. More...
__IOM uint32_t	RBAR
	Offset: 0x00C (R/W) MPU Region Base Address Register. More...
__IOM uint32_t	RASR
	Offset: 0x010 (R/W) MPU Region Attribute and Size Register. More...
__IOM uint32_t	RBAR_A1
	Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register. More...
__IOM uint32_t	RASR_A1
	Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register. More...
__IOM uint32_t	RBAR_A2
	Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register. More...
__IOM uint32_t	RASR_A2
	Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register. More...
__IOM uint32_t	RBAR_A3
	Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register. More...
__IOM uint32_t	RASR_A3
	Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register. More...

Description

Structure type to access the Memory Protection Unit (MPU).

Field Documentation

MPU_Type::CTRL

Offset: 0x004 (R/W) MPU Control Register.

Enables the MPU, and when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1.

Bits	Name	Function
[31:3]	-	Reserved.
[2]	PRIVDEFENA	0 - Disables the default memory map. 1 - Enables the default memory map as a background region for privileged access.
[1]	HFNMIENA	0 - Disables the MPU for exception handlers. 1 - Use the MPU for memory accesses by exception handlers.
[0]	ENABLE	0 - The MPU is disabled. 1 - The MPU is enabled.

MPU_Type::RASR

Offset: 0x010 (R/W) MPU Region Attribute and Size Register.

Defines the size and access behavior of the region identified by MPU_RNR, and enables that region.

Bits	Name	Function
[31:29]	-	Reserved.
[28]	XN	Execute Never.
[27]	-	Reserved.
[26:24]	AP	Access Permissions, see ARM_MPU_AP_xxx.
[23:22]	-	Reserved.
[21:19]	TEX	Type Extension.
[18]	S	Shareable.
[17]	C	Cacheable.
[16]	B	Bufferable.
[15:8]	SRD	Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled (0) or disabled (1).
[7:6]	-	Reserved.
[5:1]	SIZE	Indicates the region size. The region size, in bytes, is 2(SIZE+1). SIZE field values less than 4 are reserved, because the smallest supported region size is 32 bytes.
[0]	ENABLE	0 - This region is disabled. 1 - This region is enabled.

MPU_Type::RASR_A1

Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register.

Alias for MPU_Type::RASR.

MPU_Type::RASR_A2

Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register.

Alias for MPU_Type::RASR.

MPU_Type::RASR_A3

Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register.

Alias for MPU_Type::RASR.

MPU_Type::RBAR

Offset: 0x00C (R/W) MPU Region Base Address Register.

Holds the base address of the region identified by MPU_RNR. On a write, can also be used to update the base address of a specified region, in the range 0 to 15, updating MPU_RNR with the new region number.

Bits	Name	Function
[31:5]	ADDR	Base address of the region.
[4]	VALID	1 - Update MPU_Type::RNR to the value obtained by zero extending the REGION value specified in this write, and apply the base address update to this region.
[3:0]	REGION	On writes, can specify the number of the region to update, see VALID field description.

MPU_Type::RBAR_A1

Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register.

Alias for MPU_Type::RBAR.

MPU_Type::RBAR_A2

Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register.

Alias for MPU_Type::RBAR.

MPU_Type::RBAR_A3

Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register.

Alias for MPU_Type::RBAR.

MPU_Type::RNR

Offset: 0x008 (R/W) MPU Region RNRber Register.

Selects the region currently accessed by MPU_Type::RBAR and MPU_Type::RASR.

Bits	Name	Function
[31:8]	-	Reserved.
[7:0]	REGION	Indicates the memory region accessed.

MPU_Type::TYPE

Offset: 0x000 (R/ ) MPU Type Register.

The MPU Type Register indicates how many regions the MPU support. Software can use it to determine if the processor implements an MPU.

Bits	Name	Function
[31:24]	-	Reserved.
[23:16]	IREGION	Instruction region. RAZ. Armv7-M only supports a unified MPU.
[15:8]	DREGION	Number of regions supported by the MPU. If this field reads-as-zero the processor does not implement an MPU.
[7:1]	-	Reserved.
[0]	SEPARATE	Indicates support for separate instruction and data address maps. RAZ. Armv7-M only supports a unified MPU.