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CMSIS-Core (Cortex-M)
Version 5.6.0
CMSIS-Core support for Cortex-M processor-based devices
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CMSIS-Core (Cortex-M)
Version 5.6.0
CMSIS-Core support for Cortex-M processor-based devices
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Structure type to access the System Control Block (SCB). More...
Data Fields | |
| __IM uint32_t | CPUID |
| Offset: 0x000 (R/ ) CPUID Base Register. More... | |
| __IOM uint32_t | ICSR |
| Offset: 0x004 (R/W) Interrupt Control and State Register. More... | |
| __IOM uint32_t | VTOR |
| Offset: 0x008 (R/W) Vector Table Offset Register. More... | |
| __IOM uint32_t | AIRCR |
| Offset: 0x00C (R/W) Application Interrupt and Reset Control Register. More... | |
| __IOM uint32_t | SCR |
| Offset: 0x010 (R/W) System Control Register. More... | |
| __IOM uint32_t | CCR |
| Offset: 0x014 (R/W) Configuration Control Register. More... | |
| __IOM uint8_t | SHP [12] |
| Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) More... | |
| __IOM uint32_t | SHCSR |
| Offset: 0x024 (R/W) System Handler Control and State Register. More... | |
| __IOM uint32_t | CFSR |
| Offset: 0x028 (R/W) Configurable Fault Status Register. More... | |
| __IOM uint32_t | HFSR |
| Offset: 0x02C (R/W) HardFault Status Register. More... | |
| __IOM uint32_t | DFSR |
| Offset: 0x030 (R/W) Debug Fault Status Register. More... | |
| __IOM uint32_t | MMFAR |
| Offset: 0x034 (R/W) MemManage Fault Address Register. More... | |
| __IOM uint32_t | BFAR |
| Offset: 0x038 (R/W) BusFault Address Register. More... | |
| __IOM uint32_t | AFSR |
| Offset: 0x03C (R/W) Auxiliary Fault Status Register. More... | |
| __IM uint32_t | PFR [2] |
| Offset: 0x040 (R/ ) Processor Feature Register. More... | |
| __IM uint32_t | DFR |
| Offset: 0x048 (R/ ) Debug Feature Register. More... | |
| __IM uint32_t | ADR |
| Offset: 0x04C (R/ ) Auxiliary Feature Register. More... | |
| __IM uint32_t | MMFR [4] |
| Offset: 0x050 (R/ ) Memory Model Feature Register. More... | |
| __IM uint32_t | ISAR [5] |
| Offset: 0x060 (R/ ) Instruction Set Attributes Register. More... | |
| uint32_t | RESERVED0 [5] |
| Reserved. More... | |
| __IOM uint32_t | CPACR |
| Offset: 0x088 (R/W) Coprocessor Access Control Register. More... | |
Structure type to access the System Control Block (SCB).
| __IM uint32_t SCB_Type::ADR |
Offset: 0x04C (R/ ) Auxiliary Feature Register.
| __IOM uint32_t SCB_Type::AFSR |
Offset: 0x03C (R/W) Auxiliary Fault Status Register.
| __IOM uint32_t SCB_Type::AIRCR |
Offset: 0x00C (R/W) Application Interrupt and Reset Control Register.
| __IOM uint32_t SCB_Type::BFAR |
Offset: 0x038 (R/W) BusFault Address Register.
| __IOM uint32_t SCB_Type::CCR |
Offset: 0x014 (R/W) Configuration Control Register.
| __IOM uint32_t SCB_Type::CFSR |
Offset: 0x028 (R/W) Configurable Fault Status Register.
| __IOM uint32_t SCB_Type::CPACR |
Offset: 0x088 (R/W) Coprocessor Access Control Register.
| __IM uint32_t SCB_Type::CPUID |
Offset: 0x000 (R/ ) CPUID Base Register.
| __IM uint32_t SCB_Type::DFR |
Offset: 0x048 (R/ ) Debug Feature Register.
| __IOM uint32_t SCB_Type::DFSR |
Offset: 0x030 (R/W) Debug Fault Status Register.
| __IOM uint32_t SCB_Type::HFSR |
Offset: 0x02C (R/W) HardFault Status Register.
| __IOM uint32_t SCB_Type::ICSR |
Offset: 0x004 (R/W) Interrupt Control and State Register.
| __IM uint32_t SCB_Type::ISAR[5] |
Offset: 0x060 (R/ ) Instruction Set Attributes Register.
| __IOM uint32_t SCB_Type::MMFAR |
Offset: 0x034 (R/W) MemManage Fault Address Register.
| __IM uint32_t SCB_Type::MMFR[4] |
Offset: 0x050 (R/ ) Memory Model Feature Register.
| __IM uint32_t SCB_Type::PFR[2] |
Offset: 0x040 (R/ ) Processor Feature Register.
| uint32_t SCB_Type::RESERVED0[5] |
Reserved.
| __IOM uint32_t SCB_Type::SCR |
Offset: 0x010 (R/W) System Control Register.
| __IOM uint32_t SCB_Type::SHCSR |
Offset: 0x024 (R/W) System Handler Control and State Register.
| __IOM uint8_t SCB_Type::SHP[12] |
Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)
| __IOM uint32_t SCB_Type::VTOR |
Offset: 0x008 (R/W) Vector Table Offset Register.
