CMSIS-Core (Cortex-A)
Version 1.2.1
CMSIS-Core support for Cortex-A processor-based devices
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The ACTLR provides IMPLEMENTATION DEFINED configuration and control options. More...
Content | |
ACTLR Bits | |
Bit position and mask macros. | |
Data Structures | |
struct | ACTLR_Type |
Bit field declaration for ACTLR layout. More... | |
Functions | |
__STATIC_FORCEINLINE void | __set_ACTRL (uint32_t actrl) |
Set ACTRL. More... | |
__STATIC_FORCEINLINE uint32_t | __get_ACTLR (void) |
Get ACTLR. More... | |
The ACTLR characteristics are differs between various Armv7-A implementations.
Cortex-A5
Bits | Name | Function |
---|---|---|
[31:29] | - | Reserved. |
[28] | DBDI | Disable Branch Dual Issue |
[27:19] | - | Reserved. |
[18] | BTDIS | Disable indirect Branch Target Address Cache (BTAC). |
[17] | RSDIS | Disable return stack operation. |
[16:15] | BP | Branch prediction policy. |
[14:13] | L1PCTL | L1 Data prefetch control. |
[12] | RADIS | Disable Data Cache read-allocate mode. |
[11] | DWBST | Disable AXI data write bursts to Normal memory. |
[10] | DODMBS | Disable optimized data memory barrier behavior. |
[9:8] | - | Reserved. |
[7] | EXCL | Exclusive L1/L2 cache control. |
[6] | SMP | Enables coherent requests to the processor. |
[5:1] | - | Reserved. |
[0] | FW | Cache and TLB maintenance broadcast. |
Cortex-A7
Bits | Name | Function |
---|---|---|
[31:29] | - | Reserved. |
[28] | DDI | Disable Dual Issue |
[27:16] | - | Reserved. |
[15] | DDVM | Disable Distributed Virtual Memory transactions. |
[14:13] | L1PCTL | L1 Data prefetch control. |
[12] | L1RADIS | L1 Data Cache read-allocate mode disable. |
[11] | L2RADIS | L2 Data Cache read-allocate mode disable. |
[10] | DODMBS | Disable optimized data memory barrier behavior. |
[9:7] | - | Reserved. |
[6] | SMP | Enables coherent requests to the processor. |
[5:0] | - | Reserved. |
Cortex-A9
Bits | Name | Function |
---|---|---|
[31:10] | - | Reserved. |
[9] | PARITY | Support for parity checking, if implemented. |
[8] | AOW | Enable allocation in one cache way only. |
[7] | EXCL | Exclusive L1/L2 cache control. |
[6] | SMP | Enables coherent requests to the processor. |
[5:4] | - | Reserved. |
[3] | WFLZM | Enable write full line of zeros modea. |
[2] | L1PE | Dside prefetch. |
[1] | - | Reserved. |
[0] | FW | Cache and TLB maintenance broadcast. |
Consider using __get_ACTLR and __set_ACTRL to access ACTRL register.
__STATIC_INLINE uint32_t __get_ACTLR | ( | void | ) |
This function returns the value of the Auxiliary Control Register (ACTLR).
__STATIC_INLINE void __set_ACTRL | ( | uint32_t | actrl | ) |
[in] | actrl | Auxiliary Control Register value to set |
This function assigns the given value to the Auxiliary Control Register (ACTLR).