CMSIS-Core (Cortex-M)
Version 5.6.0
CMSIS-Core support for Cortex-M processor-based devices
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Functions to access the Cortex-M core registers. More...
Functions | |
uint32_t | __get_CONTROL (void) |
Read the CONTROL register. More... | |
void | __set_CONTROL (uint32_t control) |
Set the CONTROL Register. More... | |
uint32_t | __get_IPSR (void) |
Read the IPSR register. More... | |
uint32_t | __get_APSR (void) |
Read the APSR register. More... | |
uint32_t | __get_xPSR (void) |
Read the xPSR register. More... | |
uint32_t | __get_PSP (void) |
Read the PSP register. More... | |
void | __set_PSP (uint32_t topOfProcStack) |
Set the PSP register. More... | |
uint32_t | __get_MSP (void) |
Read the MSP register. More... | |
void | __set_MSP (uint32_t topOfMainStack) |
Set the MSP register. More... | |
uint32_t | __get_PRIMASK (void) |
Read the PRIMASK register bit. More... | |
void | __set_PRIMASK (uint32_t priMask) |
Set the Priority Mask bit. More... | |
uint32_t | __get_BASEPRI (void) |
Read the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. More... | |
void | __set_BASEPRI (uint32_t basePri) |
Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. More... | |
void | __set_BASEPRI_MAX (uint32_t basePri) |
Increase the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. More... | |
uint32_t | __get_FAULTMASK (void) |
Read the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]. More... | |
void | __set_FAULTMASK (uint32_t faultMask) |
Set the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]. More... | |
uint32_t | __get_FPSCR (void) |
Read the FPSCR register [only Cortex-M4 and Cortex-M7]. More... | |
void | __set_FPSCR (uint32_t fpscr) |
Set the FPSC register [only for Cortex-M4 and Cortex-M7]. More... | |
void | __enable_irq (void) |
Globally enables interrupts and configurable fault handlers. More... | |
void | __disable_irq (void) |
Globally disables interrupts and configurable fault handlers. More... | |
void | __enable_fault_irq (void) |
Enables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000]. More... | |
void | __disable_fault_irq (void) |
Disables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000]. More... | |
uint32_t | __get_PSPLIM (void) |
Get Process Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. More... | |
void | __set_PSPLIM (uint32_t ProcStackPtrLimit) |
Set Process Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. More... | |
uint32_t | __get_MSPLIM (void) |
Get Main Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. More... | |
__set_MSPLIM (uint32_t MainStackPtrLimit) | |
Set Main Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. More... | |
Functions to access the Cortex-M core registers.
The following functions provide access to Cortex-M core registers.
void __disable_fault_irq | ( | void | ) |
Disables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000].
The function disables interrupts and all fault handlers by setting FAULTMASK. The function uses the instruction CPSID f.
void __disable_irq | ( | void | ) |
Globally disables interrupts and configurable fault handlers.
The function disables interrupts and all configurable fault handlers by setting PRIMASK. The function uses the instruction CPSID i.
void __enable_fault_irq | ( | void | ) |
Enables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000].
The function enables interrupts and all fault handlers by clearing FAULTMASK. The function uses the instruction CPSIE f.
void __enable_irq | ( | void | ) |
Globally enables interrupts and configurable fault handlers.
The function enables interrupts and all configurable fault handlers by clearing PRIMASK. The function uses the instruction CPSIE i.
uint32_t __get_APSR | ( | void | ) |
Read the APSR register.
The function reads the Application Program Status Register (APSR) using the instruction MRS.
The APSR contains the current state of the condition flags from instructions executed previously. The APSR is essential for controlling conditional branches. The following flags are used:
SEL
instruction to perform byte-based selection from two registers.uint32_t __get_BASEPRI | ( | void | ) |
Read the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000].
The function returns the Base Priority Mask register (BASEPRI) using the instruction MRS.
BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.
uint32_t __get_CONTROL | ( | void | ) |
Read the CONTROL register.
The function reads the CONTROL register value using the instruction MRS.
The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits:
uint32_t __get_FAULTMASK | ( | void | ) |
Read the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000].
The function reads the Fault Mask register (FAULTMASK) value using the instruction MRS.
FAULTMASK prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI).
uint32_t __get_FPSCR | ( | void | ) |
Read the FPSCR register [only Cortex-M4 and Cortex-M7].
The function reads the Floating-Point Status Control Register (FPSCR) value.
FPSCR provides all necessary User level controls of the floating-point system.
uint32_t __get_IPSR | ( | void | ) |
Read the IPSR register.
The function reads the Interrupt Program Status Register (IPSR) using the instruction MRS.
The ISPR contains the exception type number of the current Interrupt Service Routine (ISR). Each exception has an associated unique IRQn number. The following bits are used:
uint32_t __get_MSP | ( | void | ) |
Read the MSP register.
The function reads the Main Stack Pointer (MSP) value using the instruction MRS.
Physically two different stack pointers (SP) exist:
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
uint32_t __get_MSPLIM | ( | void | ) |
Get Main Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode.
Returns the current value of the Main Stack Pointer Limit (MSPLIM).
uint32_t __get_PRIMASK | ( | void | ) |
Read the PRIMASK register bit.
The function reads the Priority Mask register (PRIMASK) value using the instruction MRS.
PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.
uint32_t __get_PSP | ( | void | ) |
Read the PSP register.
The function reads the Process Stack Pointer (PSP) value using the instruction MRS.
Physically two different stack pointers (SP) exist:
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
uint32_t __get_PSPLIM | ( | void | ) |
Get Process Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode.
Returns the current value of the Process Stack Pointer Limit (PSPLIM).
uint32_t __get_xPSR | ( | void | ) |
Read the xPSR register.
The function reads the combined Program Status Register (xPSR) using the instruction MRS.
xPSR provides information about program execution and the APSR flags. It consists of the following PSRs:
In addition to the flags described in __get_APSR and __get_IPSR, the register provides the following flags:
void __set_BASEPRI | ( | uint32_t | basePri | ) |
Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000].
The function sets the Base Priority Mask register (BASEPRI) value using the instruction MSR.
BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.
[in] | basePri | BASEPRI value to set |
void __set_BASEPRI_MAX | ( | uint32_t | basePri | ) |
Increase the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000].
The function only increases the Base Priority Mask register (BASEPRI) value using the instruction MSR. The value is set only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level.
BASEPRI defines the minimum priority for exception processing.
[in] | basePri | BASEPRI value to set |
void __set_CONTROL | ( | uint32_t | control | ) |
Set the CONTROL Register.
The function sets the CONTROL register value using the instruction MSR.
The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits:
[in] | control | CONTROL register value to set |
void __set_FAULTMASK | ( | uint32_t | faultMask | ) |
Set the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000].
The function sets the Fault Mask register (FAULTMASK) value using the instruction MSR.
FAULTMASK prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). FAULTMASK can be used to escalate a configurable fault handler (BusFault, usage fault, or memory management fault) to hard fault level without invoking a hard fault. This allows the fault handler to pretend to be the hard fault handler, with the ability to:
[in] | faultMask | FAULTMASK register value to set |
void __set_FPSCR | ( | uint32_t | fpscr | ) |
Set the FPSC register [only for Cortex-M4 and Cortex-M7].
The function sets the Floating-Point Status Control Register (FPSCR) value.
FPSCR provides all necessary User level control of the floating-point system.
[in] | fpscr | FPSCR value to set |
void __set_MSP | ( | uint32_t | topOfMainStack | ) |
Set the MSP register.
The function sets the Main Stack Pointer (MSP) value using the instruction MSR.
Physically two different stack pointers (SP) exist:
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
[in] | topOfMainStack | MSP value to set |
__set_MSPLIM | ( | uint32_t | MainStackPtrLimit | ) |
Set Main Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode.
Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
[in] | MainStackPtrLimit | Main Stack Pointer Limit value to set |
void __set_PRIMASK | ( | uint32_t | priMask | ) |
Set the Priority Mask bit.
The function sets the Priority Mask register (PRIMASK) value using the instruction MSR.
PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.
[in] | priMask | Priority Mask
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void __set_PSP | ( | uint32_t | topOfProcStack | ) |
Set the PSP register.
The function sets the Process Stack Pointer (PSP) value using the instruction MSR.
Physically two different stack pointers (SP) exist:
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
[in] | topOfProcStack | PSP value to set |
void __set_PSPLIM | ( | uint32_t | ProcStackPtrLimit | ) |
Set Process Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode.
Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
[in] | ProcStackPtrLimit | Process Stack Pointer Limit value to set |