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CMSIS-Core (Cortex-M)
Version 5.6.0
CMSIS-Core support for Cortex-M processor-based devices
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CMSIS-Core (Cortex-M)
Version 5.6.0
CMSIS-Core support for Cortex-M processor-based devices
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IDs for additional events defined for Cortex-M85. More...
Macros | |
| #define | ARMCM85_PMU_ECC_ERR 0xC000 |
| Any ECC error. More... | |
| #define | ARMCM85_PMU_ECC_ERR_MBIT 0xC001 |
| Any multi-bit ECC error. More... | |
| #define | ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 |
| Any ECC error in the data cache. More... | |
| #define | ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 |
| Any ECC error in the instruction cache. More... | |
| #define | ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 |
| Any multi-bit ECC error in the data cache. More... | |
| #define | ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 |
| Any multi-biy ECC error in the instruction cache. More... | |
| #define | ARMCM85_PMU_ECC_ERR_DTCM 0xC020 |
| Any ECC error in the DTCM. More... | |
| #define | ARMCM85_PMU_ECC_ERR_ITCM 0xC021 |
| Any ECC error in the ITCM. More... | |
| #define | ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 |
| Any multi-bit ECC error in the DTCM. More... | |
| #define | ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 |
| Any multi-bit ECC error in the ITCM. More... | |
| #define | ARMCM85_PMU_PF_LINEFILL 0xC100 |
| A prefetcher starts a line-fill. More... | |
| #define | ARMCM85_PMU_PF_CANCEL 0xC101 |
| A prefetcher stops prefetching. More... | |
| #define | ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 |
| A linefill triggered by a prefetcher has been dropped because of lack of buffering. More... | |
| #define | ARMCM85_PMU_NWAMODE_ENTER 0xC200 |
| No write-allocate mode entry. More... | |
| #define | ARMCM85_PMU_NWAMODE 0xC201 |
| Write-allocate store is not allocated into the data cache due to no-write-allocate mode. More... | |
| #define | ARMCM85_PMU_SAHB_ACCESS 0xC300 |
| Read or write access on the S-AHB interface to the TCM. More... | |
| #define | ARMCM85_PMU_PAHB_ACCESS 0xC301 |
| Read or write access on the P-AHB interface. More... | |
| #define | ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 |
| Any beat access to M-AXI write interface. More... | |
| #define | ARMCM85_PMU_AXI_READ_ACCESS 0xC303 |
| Any beat access to M-AXI read interface. More... | |
| #define | ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 |
| Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress. More... | |
| #define | ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 |
| Denial of Service timeout has fired three times and blocked the LSU to force forward progress. More... | |
IDs for additional events defined for Cortex-M85.
These events are available on a Cortex-M85 device including a PMU.
| #define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 |
Any beat access to M-AXI read interface.
| #define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 |
Any beat access to M-AXI write interface.
| #define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 |
Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress.
| #define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 |
Denial of Service timeout has fired three times and blocked the LSU to force forward progress.
| #define ARMCM85_PMU_ECC_ERR 0xC000 |
Any ECC error.
| #define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 |
Any ECC error in the data cache.
| #define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 |
Any ECC error in the DTCM.
| #define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 |
Any ECC error in the instruction cache.
| #define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 |
Any ECC error in the ITCM.
| #define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 |
Any multi-bit ECC error.
| #define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 |
Any multi-bit ECC error in the data cache.
| #define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 |
Any multi-bit ECC error in the DTCM.
| #define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 |
Any multi-biy ECC error in the instruction cache.
| #define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 |
Any multi-bit ECC error in the ITCM.
| #define ARMCM85_PMU_NWAMODE 0xC201 |
Write-allocate store is not allocated into the data cache due to no-write-allocate mode.
| #define ARMCM85_PMU_NWAMODE_ENTER 0xC200 |
No write-allocate mode entry.
| #define ARMCM85_PMU_PAHB_ACCESS 0xC301 |
Read or write access on the P-AHB interface.
| #define ARMCM85_PMU_PF_CANCEL 0xC101 |
A prefetcher stops prefetching.
| #define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 |
A linefill triggered by a prefetcher has been dropped because of lack of buffering.
| #define ARMCM85_PMU_PF_LINEFILL 0xC100 |
A prefetcher starts a line-fill.
| #define ARMCM85_PMU_SAHB_ACCESS 0xC300 |
Read or write access on the S-AHB interface to the TCM.
