Data Structures
struct	CPSR_Type
	Bit field declaration for CPSR layout. More...

struct	SCTLR_Type
	Bit field declaration for SCTLR layout. More...

struct	ACTLR_Type
	Bit field declaration for ACTLR layout. More...

struct	CPACR_Type
	Bit field declaration for CPACR layout. More...

struct	DFSR_Type
	Bit field declaration for DFSR layout. More...

struct	IFSR_Type
	Bit field declaration for IFSR layout. More...

struct	ISR_Type
	Bit field declaration for ISR layout. More...

struct	L2C_310_TypeDef
	Union type to access the L2C_310 Cache Controller. More...

struct	GICDistributor_Type
	Structure type to access the Generic Interrupt Controller Distributor (GICD) More...

struct	GICInterface_Type
	Structure type to access the Generic Interrupt Controller Interface (GICC) More...

struct	Timer_Type
	Structure type to access the Private Timer. More...

union	CNTP_CTL_Type
	Physical Timer Control register. More...

struct	mmu_region_attributes_Type

Macros
#define	__FPU_USED 0U

#define	__CORE_CA_H_DEPENDANT

#define	__FPU_PRESENT 0U

#define	__GIC_PRESENT 1U

#define	__TIM_PRESENT 1U

#define	__I volatile
	Defines 'read only' permissions.

#define	__O volatile
	Defines 'write only' permissions.

#define	__IO volatile
	Defines 'read / write' permissions.

#define	__IM volatile const
	Defines 'read only' structure member permissions.

#define	__OM volatile
	Defines 'write only' structure member permissions.

#define	__IOM volatile
	Defines 'read / write' structure member permissions.

#define	RESERVED(N, T) T RESERVED##N;

#define	CPSR_N_Pos 31U
	CPSR: N Position.

#define	CPSR_N_Msk (1UL << CPSR_N_Pos)
	CPSR: N Mask.

#define	CPSR_Z_Pos 30U
	CPSR: Z Position.

#define	CPSR_Z_Msk (1UL << CPSR_Z_Pos)
	CPSR: Z Mask.

#define	CPSR_C_Pos 29U
	CPSR: C Position.

#define	CPSR_C_Msk (1UL << CPSR_C_Pos)
	CPSR: C Mask.

#define	CPSR_V_Pos 28U
	CPSR: V Position.

#define	CPSR_V_Msk (1UL << CPSR_V_Pos)
	CPSR: V Mask.

#define	CPSR_Q_Pos 27U
	CPSR: Q Position.

#define	CPSR_Q_Msk (1UL << CPSR_Q_Pos)
	CPSR: Q Mask.

#define	CPSR_IT0_Pos 25U
	CPSR: IT0 Position.

#define	CPSR_IT0_Msk (3UL << CPSR_IT0_Pos)
	CPSR: IT0 Mask.

#define	CPSR_J_Pos 24U
	CPSR: J Position.

#define	CPSR_J_Msk (1UL << CPSR_J_Pos)
	CPSR: J Mask.

#define	CPSR_GE_Pos 16U
	CPSR: GE Position.

#define	CPSR_GE_Msk (0xFUL << CPSR_GE_Pos)
	CPSR: GE Mask.

#define	CPSR_IT1_Pos 10U
	CPSR: IT1 Position.

#define	CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos)
	CPSR: IT1 Mask.

#define	CPSR_E_Pos 9U
	CPSR: E Position.

#define	CPSR_E_Msk (1UL << CPSR_E_Pos)
	CPSR: E Mask.

#define	CPSR_A_Pos 8U
	CPSR: A Position.

#define	CPSR_A_Msk (1UL << CPSR_A_Pos)
	CPSR: A Mask.

#define	CPSR_I_Pos 7U
	CPSR: I Position.

#define	CPSR_I_Msk (1UL << CPSR_I_Pos)
	CPSR: I Mask.

#define	CPSR_F_Pos 6U
	CPSR: F Position.

#define	CPSR_F_Msk (1UL << CPSR_F_Pos)
	CPSR: F Mask.

#define	CPSR_T_Pos 5U
	CPSR: T Position.

#define	CPSR_T_Msk (1UL << CPSR_T_Pos)
	CPSR: T Mask.

#define	CPSR_M_Pos 0U
	CPSR: M Position.

#define	CPSR_M_Msk (0x1FUL << CPSR_M_Pos)
	CPSR: M Mask.

#define	CPSR_M_USR 0x10U
	CPSR: M User mode (PL0)

#define	CPSR_M_FIQ 0x11U
	CPSR: M Fast Interrupt mode (PL1)

#define	CPSR_M_IRQ 0x12U
	CPSR: M Interrupt mode (PL1)

#define	CPSR_M_SVC 0x13U
	CPSR: M Supervisor mode (PL1)

#define	CPSR_M_MON 0x16U
	CPSR: M Monitor mode (PL1)

#define	CPSR_M_ABT 0x17U
	CPSR: M Abort mode (PL1)

#define	CPSR_M_HYP 0x1AU
	CPSR: M Hypervisor mode (PL2)

#define	CPSR_M_UND 0x1BU
	CPSR: M Undefined mode (PL1)

#define	CPSR_M_SYS 0x1FU
	CPSR: M System mode (PL1)

#define	SCTLR_TE_Pos 30U
	SCTLR: TE Position.

#define	SCTLR_TE_Msk (1UL << SCTLR_TE_Pos)
	SCTLR: TE Mask.

#define	SCTLR_AFE_Pos 29U
	SCTLR: AFE Position.

#define	SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos)
	SCTLR: AFE Mask.

#define	SCTLR_TRE_Pos 28U
	SCTLR: TRE Position.

#define	SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos)
	SCTLR: TRE Mask.

#define	SCTLR_NMFI_Pos 27U
	SCTLR: NMFI Position.

#define	SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos)
	SCTLR: NMFI Mask.

#define	SCTLR_EE_Pos 25U
	SCTLR: EE Position.

#define	SCTLR_EE_Msk (1UL << SCTLR_EE_Pos)
	SCTLR: EE Mask.

#define	SCTLR_VE_Pos 24U
	SCTLR: VE Position.

#define	SCTLR_VE_Msk (1UL << SCTLR_VE_Pos)
	SCTLR: VE Mask.

#define	SCTLR_U_Pos 22U
	SCTLR: U Position.

#define	SCTLR_U_Msk (1UL << SCTLR_U_Pos)
	SCTLR: U Mask.

#define	SCTLR_FI_Pos 21U
	SCTLR: FI Position.

#define	SCTLR_FI_Msk (1UL << SCTLR_FI_Pos)
	SCTLR: FI Mask.

#define	SCTLR_UWXN_Pos 20U
	SCTLR: UWXN Position.

#define	SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos)
	SCTLR: UWXN Mask.

#define	SCTLR_WXN_Pos 19U
	SCTLR: WXN Position.

#define	SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos)
	SCTLR: WXN Mask.

#define	SCTLR_HA_Pos 17U
	SCTLR: HA Position.

#define	SCTLR_HA_Msk (1UL << SCTLR_HA_Pos)
	SCTLR: HA Mask.

#define	SCTLR_RR_Pos 14U
	SCTLR: RR Position.

#define	SCTLR_RR_Msk (1UL << SCTLR_RR_Pos)
	SCTLR: RR Mask.

#define	SCTLR_V_Pos 13U
	SCTLR: V Position.

#define	SCTLR_V_Msk (1UL << SCTLR_V_Pos)
	SCTLR: V Mask.

#define	SCTLR_I_Pos 12U
	SCTLR: I Position.

#define	SCTLR_I_Msk (1UL << SCTLR_I_Pos)
	SCTLR: I Mask.

#define	SCTLR_Z_Pos 11U
	SCTLR: Z Position.

#define	SCTLR_Z_Msk (1UL << SCTLR_Z_Pos)
	SCTLR: Z Mask.

#define	SCTLR_SW_Pos 10U
	SCTLR: SW Position.

#define	SCTLR_SW_Msk (1UL << SCTLR_SW_Pos)
	SCTLR: SW Mask.

#define	SCTLR_B_Pos 7U
	SCTLR: B Position.

#define	SCTLR_B_Msk (1UL << SCTLR_B_Pos)
	SCTLR: B Mask.

#define	SCTLR_CP15BEN_Pos 5U
	SCTLR: CP15BEN Position.

#define	SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos)
	SCTLR: CP15BEN Mask.

#define	SCTLR_C_Pos 2U
	SCTLR: C Position.

#define	SCTLR_C_Msk (1UL << SCTLR_C_Pos)
	SCTLR: C Mask.

#define	SCTLR_A_Pos 1U
	SCTLR: A Position.

#define	SCTLR_A_Msk (1UL << SCTLR_A_Pos)
	SCTLR: A Mask.

#define	SCTLR_M_Pos 0U
	SCTLR: M Position.

#define	SCTLR_M_Msk (1UL << SCTLR_M_Pos)
	SCTLR: M Mask.

#define	ACTLR_DDI_Pos 28U
	ACTLR: DDI Position.

#define	ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos)
	ACTLR: DDI Mask.

#define	ACTLR_DBDI_Pos 28U
	ACTLR: DBDI Position.

#define	ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos)
	ACTLR: DBDI Mask.

#define	ACTLR_BTDIS_Pos 18U
	ACTLR: BTDIS Position.

#define	ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos)
	ACTLR: BTDIS Mask.

#define	ACTLR_RSDIS_Pos 17U
	ACTLR: RSDIS Position.

#define	ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos)
	ACTLR: RSDIS Mask.

#define	ACTLR_BP_Pos 15U
	ACTLR: BP Position.

#define	ACTLR_BP_Msk (3UL << ACTLR_BP_Pos)
	ACTLR: BP Mask.

#define	ACTLR_DDVM_Pos 15U
	ACTLR: DDVM Position.

#define	ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos)
	ACTLR: DDVM Mask.

#define	ACTLR_L1PCTL_Pos 13U
	ACTLR: L1PCTL Position.

#define	ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos)
	ACTLR: L1PCTL Mask.

#define	ACTLR_RADIS_Pos 12U
	ACTLR: RADIS Position.

#define	ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos)
	ACTLR: RADIS Mask.

#define	ACTLR_L1RADIS_Pos 12U
	ACTLR: L1RADIS Position.

#define	ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos)
	ACTLR: L1RADIS Mask.

#define	ACTLR_DWBST_Pos 11U
	ACTLR: DWBST Position.

#define	ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos)
	ACTLR: DWBST Mask.

#define	ACTLR_L2RADIS_Pos 11U
	ACTLR: L2RADIS Position.

#define	ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos)
	ACTLR: L2RADIS Mask.

#define	ACTLR_DODMBS_Pos 10U
	ACTLR: DODMBS Position.

#define	ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos)
	ACTLR: DODMBS Mask.

#define	ACTLR_PARITY_Pos 9U
	ACTLR: PARITY Position.

#define	ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos)
	ACTLR: PARITY Mask.

#define	ACTLR_AOW_Pos 8U
	ACTLR: AOW Position.

#define	ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos)
	ACTLR: AOW Mask.

#define	ACTLR_EXCL_Pos 7U
	ACTLR: EXCL Position.

#define	ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos)
	ACTLR: EXCL Mask.

#define	ACTLR_SMP_Pos 6U
	ACTLR: SMP Position.

#define	ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos)
	ACTLR: SMP Mask.

#define	ACTLR_WFLZM_Pos 3U
	ACTLR: WFLZM Position.

#define	ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos)
	ACTLR: WFLZM Mask.

#define	ACTLR_L1PE_Pos 2U
	ACTLR: L1PE Position.

#define	ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos)
	ACTLR: L1PE Mask.

#define	ACTLR_FW_Pos 0U
	ACTLR: FW Position.

#define	ACTLR_FW_Msk (1UL << ACTLR_FW_Pos)
	ACTLR: FW Mask.

#define	CPACR_ASEDIS_Pos 31U
	CPACR: ASEDIS Position.

#define	CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos)
	CPACR: ASEDIS Mask.

#define	CPACR_D32DIS_Pos 30U
	CPACR: D32DIS Position.

#define	CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos)
	CPACR: D32DIS Mask.

#define	CPACR_TRCDIS_Pos 28U
	CPACR: D32DIS Position.

#define	CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos)
	CPACR: D32DIS Mask.

#define	CPACR_CP_Pos_(n) (n*2U)
	CPACR: CPn Position.

#define	CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n))
	CPACR: CPn Mask.

#define	CPACR_CP_NA 0U
	CPACR CPn field: Access denied.

#define	CPACR_CP_PL1 1U
	CPACR CPn field: Accessible from PL1 only.

#define	CPACR_CP_FA 3U
	CPACR CPn field: Full access.

#define	DFSR_CM_Pos 13U
	DFSR: CM Position.

#define	DFSR_CM_Msk (1UL << DFSR_CM_Pos)
	DFSR: CM Mask.

#define	DFSR_Ext_Pos 12U
	DFSR: Ext Position.

#define	DFSR_Ext_Msk (1UL << DFSR_Ext_Pos)
	DFSR: Ext Mask.

#define	DFSR_WnR_Pos 11U
	DFSR: WnR Position.

#define	DFSR_WnR_Msk (1UL << DFSR_WnR_Pos)
	DFSR: WnR Mask.

#define	DFSR_FS1_Pos 10U
	DFSR: FS1 Position.

#define	DFSR_FS1_Msk (1UL << DFSR_FS1_Pos)
	DFSR: FS1 Mask.

#define	DFSR_LPAE_Pos 9U
	DFSR: LPAE Position.

#define	DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos)
	DFSR: LPAE Mask.

#define	DFSR_Domain_Pos 4U
	DFSR: Domain Position.

#define	DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos)
	DFSR: Domain Mask.

#define	DFSR_FS0_Pos 0U
	DFSR: FS0 Position.

#define	DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos)
	DFSR: FS0 Mask.

#define	DFSR_STATUS_Pos 0U
	DFSR: STATUS Position.

#define	DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos)
	DFSR: STATUS Mask.

#define	IFSR_ExT_Pos 12U
	IFSR: ExT Position.

#define	IFSR_ExT_Msk (1UL << IFSR_ExT_Pos)
	IFSR: ExT Mask.

#define	IFSR_FS1_Pos 10U
	IFSR: FS1 Position.

#define	IFSR_FS1_Msk (1UL << IFSR_FS1_Pos)
	IFSR: FS1 Mask.

#define	IFSR_LPAE_Pos 9U
	IFSR: LPAE Position.

#define	IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos)
	IFSR: LPAE Mask.

#define	IFSR_FS0_Pos 0U
	IFSR: FS0 Position.

#define	IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos)
	IFSR: FS0 Mask.

#define	IFSR_STATUS_Pos 0U
	IFSR: STATUS Position.

#define	IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos)
	IFSR: STATUS Mask.

#define	ISR_A_Pos 13U
	ISR: A Position.

#define	ISR_A_Msk (1UL << ISR_A_Pos)
	ISR: A Mask.

#define	ISR_I_Pos 12U
	ISR: I Position.

#define	ISR_I_Msk (1UL << ISR_I_Pos)
	ISR: I Mask.

#define	ISR_F_Pos 11U
	ISR: F Position.

#define	ISR_F_Msk (1UL << ISR_F_Pos)
	ISR: F Mask.

#define	DACR_D_Pos_(n) (2U*n)
	DACR: Dn Position.

#define	DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n))
	DACR: Dn Mask.

#define	DACR_Dn_NOACCESS 0U
	DACR Dn field: No access.

#define	DACR_Dn_CLIENT 1U
	DACR Dn field: Client.

#define	DACR_Dn_MANAGER 3U
	DACR Dn field: Manager.

#define	_VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
	Mask and shift a bit field value for use in a register bit range.

#define	_FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
	Mask and shift a register value to extract a bit filed value.

#define	L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE)
	L2C_310 register set access pointer.

#define	GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE )
	GIC Distributor register set access pointer.

#define	GICDistributor_CTLR_EnableGrp0_Pos 0U

#define	GICDistributor_CTLR_EnableGrp0_Msk (0x1U /<< GICDistributor_CTLR_EnableGrp0_Pos/)

#define	GICDistributor_CTLR_EnableGrp0(x) (((uint32_t)(((uint32_t)(x)) /<< GICDistributor_CTLR_EnableGrp0_Pos/)) & GICDistributor_CTLR_EnableGrp0_Msk)

#define	GICDistributor_CTLR_EnableGrp1_Pos 1U

#define	GICDistributor_CTLR_EnableGrp1_Msk (0x1U << GICDistributor_CTLR_EnableGrp1_Pos)

#define	GICDistributor_CTLR_EnableGrp1(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_EnableGrp1_Pos)) & GICDistributor_CTLR_EnableGrp1_Msk)

#define	GICDistributor_CTLR_ARE_Pos 4U

#define	GICDistributor_CTLR_ARE_Msk (0x1U << GICDistributor_CTLR_ARE_Pos)

#define	GICDistributor_CTLR_ARE(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_ARE_Pos)) & GICDistributor_CTLR_ARE_Msk)

#define	GICDistributor_CTLR_DC_Pos 6U

#define	GICDistributor_CTLR_DC_Msk (0x1U << GICDistributor_CTLR_DC_Pos)

#define	GICDistributor_CTLR_DC(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_DC_Pos)) & GICDistributor_CTLR_DC_Msk)

#define	GICDistributor_CTLR_EINWF_Pos 7U

#define	GICDistributor_CTLR_EINWF_Msk (0x1U << GICDistributor_CTLR_EINWF_Pos)

#define	GICDistributor_CTLR_EINWF(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_EINWF_Pos)) & GICDistributor_CTLR_EINWF_Msk)

#define	GICDistributor_CTLR_RWP_Pos 31U

#define	GICDistributor_CTLR_RWP_Msk (0x1U << GICDistributor_CTLR_RWP_Pos)

#define	GICDistributor_CTLR_RWP(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_RWP_Pos)) & GICDistributor_CTLR_RWP_Msk)

#define	GICDistributor_TYPER_ITLinesNumber_Pos 0U

#define	GICDistributor_TYPER_ITLinesNumber_Msk (0x1FU /<< GICDistributor_TYPER_ITLinesNumber_Pos/)

#define	GICDistributor_TYPER_ITLinesNumber(x) (((uint32_t)(((uint32_t)(x)) /<< GICDistributor_TYPER_ITLinesNumber_Pos/)) & GICDistributor_CTLR_ITLinesNumber_Msk)

#define	GICDistributor_TYPER_CPUNumber_Pos 5U

#define	GICDistributor_TYPER_CPUNumber_Msk (0x7U << GICDistributor_TYPER_CPUNumber_Pos)

#define	GICDistributor_TYPER_CPUNumber(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_CPUNumber_Pos)) & GICDistributor_TYPER_CPUNumber_Msk)

#define	GICDistributor_TYPER_SecurityExtn_Pos 10U

#define	GICDistributor_TYPER_SecurityExtn_Msk (0x1U << GICDistributor_TYPER_SecurityExtn_Pos)

#define	GICDistributor_TYPER_SecurityExtn(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_SecurityExtn_Pos)) & GICDistributor_TYPER_SecurityExtn_Msk)

#define	GICDistributor_TYPER_LSPI_Pos 11U

#define	GICDistributor_TYPER_LSPI_Msk (0x1FU << GICDistributor_TYPER_LSPI_Pos)

#define	GICDistributor_TYPER_LSPI(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_LSPI_Pos)) & GICDistributor_TYPER_LSPI_Msk)

#define	GICDistributor_IIDR_Implementer_Pos 0U

#define	GICDistributor_IIDR_Implementer_Msk (0xFFFU /<< GICDistributor_IIDR_Implementer_Pos/)

#define	GICDistributor_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) /<< GICDistributor_IIDR_Implementer_Pos/)) & GICDistributor_IIDR_Implementer_Msk)

#define	GICDistributor_IIDR_Revision_Pos 12U

#define	GICDistributor_IIDR_Revision_Msk (0xFU << GICDistributor_IIDR_Revision_Pos)

#define	GICDistributor_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_Revision_Pos)) & GICDistributor_IIDR_Revision_Msk)

#define	GICDistributor_IIDR_Variant_Pos 16U

#define	GICDistributor_IIDR_Variant_Msk (0xFU << GICDistributor_IIDR_Variant_Pos)

#define	GICDistributor_IIDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_Variant_Pos)) & GICDistributor_IIDR_Variant_Msk)

#define	GICDistributor_IIDR_ProductID_Pos 24U

#define	GICDistributor_IIDR_ProductID_Msk (0xFFU << GICDistributor_IIDR_ProductID_Pos)

#define	GICDistributor_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_ProductID_Pos)) & GICDistributor_IIDR_ProductID_Msk)

#define	GICDistributor_STATUSR_RRD_Pos 0U

#define	GICDistributor_STATUSR_RRD_Msk (0x1U /<< GICDistributor_STATUSR_RRD_Pos/)

#define	GICDistributor_STATUSR_RRD(x) (((uint32_t)(((uint32_t)(x)) /<< GICDistributor_STATUSR_RRD_Pos/)) & GICDistributor_STATUSR_RRD_Msk)

#define	GICDistributor_STATUSR_WRD_Pos 1U

#define	GICDistributor_STATUSR_WRD_Msk (0x1U << GICDistributor_STATUSR_WRD_Pos)

#define	GICDistributor_STATUSR_WRD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_WRD_Pos)) & GICDistributor_STATUSR_WRD_Msk)

#define	GICDistributor_STATUSR_RWOD_Pos 2U

#define	GICDistributor_STATUSR_RWOD_Msk (0x1U << GICDistributor_STATUSR_RWOD_Pos)

#define	GICDistributor_STATUSR_RWOD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_RWOD_Pos)) & GICDistributor_STATUSR_RWOD_Msk)

#define	GICDistributor_STATUSR_WROD_Pos 3U

#define	GICDistributor_STATUSR_WROD_Msk (0x1U << GICDistributor_STATUSR_WROD_Pos)

#define	GICDistributor_STATUSR_WROD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_WROD_Pos)) & GICDistributor_STATUSR_WROD_Msk)

#define	GICDistributor_SETSPI_NSR_INTID_Pos 0U

#define	GICDistributor_SETSPI_NSR_INTID_Msk (0x3FFU /<< GICDistributor_SETSPI_NSR_INTID_Pos/)

#define	GICDistributor_SETSPI_NSR_INTID(x) (((uint32_t)(((uint32_t)(x)) /<< GICDistributor_SETSPI_NSR_INTID_Pos/)) & GICDistributor_SETSPI_NSR_INTID_Msk)

#define	GICDistributor_CLRSPI_NSR_INTID_Pos 0U

#define	GICDistributor_CLRSPI_NSR_INTID_Msk (0x3FFU /<< GICDistributor_CLRSPI_NSR_INTID_Pos/)

#define	GICDistributor_CLRSPI_NSR_INTID(x) (((uint32_t)(((uint32_t)(x)) /<< GICDistributor_CLRSPI_NSR_INTID_Pos/)) & GICDistributor_CLRSPI_NSR_INTID_Msk)

#define	GICDistributor_SETSPI_SR_INTID_Pos 0U

#define	GICDistributor_SETSPI_SR_INTID_Msk (0x3FFU /<< GICDistributor_SETSPI_SR_INTID_Pos/)

#define	GICDistributor_SETSPI_SR_INTID(x) (((uint32_t)(((uint32_t)(x)) /<< GICDistributor_SETSPI_SR_INTID_Pos/)) & GICDistributor_SETSPI_SR_INTID_Msk)

#define	GICDistributor_CLRSPI_SR_INTID_Pos 0U

#define	GICDistributor_CLRSPI_SR_INTID_Msk (0x3FFU /<< GICDistributor_CLRSPI_SR_INTID_Pos/)

#define	GICDistributor_CLRSPI_SR_INTID(x) (((uint32_t)(((uint32_t)(x)) /<< GICDistributor_CLRSPI_SR_INTID_Pos/)) & GICDistributor_CLRSPI_SR_INTID_Msk)

#define	GICDistributor_ITARGETSR_CPU0_Pos 0U

#define	GICDistributor_ITARGETSR_CPU0_Msk (0x1U /<< GICDistributor_ITARGETSR_CPU0_Pos/)

#define	GICDistributor_ITARGETSR_CPU0(x) (((uint8_t)(((uint8_t)(x)) /<< GICDistributor_ITARGETSR_CPU0_Pos/)) & GICDistributor_ITARGETSR_CPU0_Msk)

#define	GICDistributor_ITARGETSR_CPU1_Pos 1U

#define	GICDistributor_ITARGETSR_CPU1_Msk (0x1U << GICDistributor_ITARGETSR_CPU1_Pos)

#define	GICDistributor_ITARGETSR_CPU1(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU1_Pos)) & GICDistributor_ITARGETSR_CPU1_Msk)

#define	GICDistributor_ITARGETSR_CPU2_Pos 2U

#define	GICDistributor_ITARGETSR_CPU2_Msk (0x1U << GICDistributor_ITARGETSR_CPU2_Pos)

#define	GICDistributor_ITARGETSR_CPU2(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU2_Pos)) & GICDistributor_ITARGETSR_CPU2_Msk)

#define	GICDistributor_ITARGETSR_CPU3_Pos 3U

#define	GICDistributor_ITARGETSR_CPU3_Msk (0x1U << GICDistributor_ITARGETSR_CPU3_Pos)

#define	GICDistributor_ITARGETSR_CPU3(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU3_Pos)) & GICDistributor_ITARGETSR_CPU3_Msk)

#define	GICDistributor_ITARGETSR_CPU4_Pos 4U

#define	GICDistributor_ITARGETSR_CPU4_Msk (0x1U << GICDistributor_ITARGETSR_CPU4_Pos)

#define	GICDistributor_ITARGETSR_CPU4(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU4_Pos)) & GICDistributor_ITARGETSR_CPU4_Msk)

#define	GICDistributor_ITARGETSR_CPU5_Pos 5U

#define	GICDistributor_ITARGETSR_CPU5_Msk (0x1U << GICDistributor_ITARGETSR_CPU5_Pos)

#define	GICDistributor_ITARGETSR_CPU5(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU5_Pos)) & GICDistributor_ITARGETSR_CPU5_Msk)

#define	GICDistributor_ITARGETSR_CPU6_Pos 6U

#define	GICDistributor_ITARGETSR_CPU6_Msk (0x1U << GICDistributor_ITARGETSR_CPU6_Pos)

#define	GICDistributor_ITARGETSR_CPU6(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU6_Pos)) & GICDistributor_ITARGETSR_CPU6_Msk)

#define	GICDistributor_ITARGETSR_CPU7_Pos 7U

#define	GICDistributor_ITARGETSR_CPU7_Msk (0x1U << GICDistributor_ITARGETSR_CPU7_Pos)

#define	GICDistributor_ITARGETSR_CPU7(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU7_Pos)) & GICDistributor_ITARGETSR_CPU7_Msk)

#define	GICDistributor_SGIR_INTID_Pos 0U

#define	GICDistributor_SGIR_INTID_Msk (0x7U /<< GICDistributor_SGIR_INTID_Pos/)

#define	GICDistributor_SGIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /<< GICDistributor_SGIR_INTID_Pos/)) & GICDistributor_SGIR_INTID_Msk)

#define	GICDistributor_SGIR_NSATT_Pos 15U

#define	GICDistributor_SGIR_NSATT_Msk (0x1U << GICDistributor_SGIR_NSATT_Pos)

#define	GICDistributor_SGIR_NSATT(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_NSATT_Pos)) & GICDistributor_SGIR_NSATT_Msk)

#define	GICDistributor_SGIR_CPUTargetList_Pos 16U

#define	GICDistributor_SGIR_CPUTargetList_Msk (0xFFU << GICDistributor_SGIR_CPUTargetList_Pos)

#define	GICDistributor_SGIR_CPUTargetList(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_CPUTargetList_Pos)) & GICDistributor_SGIR_CPUTargetList_Msk)

#define	GICDistributor_SGIR_TargetFilterList_Pos 24U

#define	GICDistributor_SGIR_TargetFilterList_Msk (0x3U << GICDistributor_SGIR_TargetFilterList_Pos)

#define	GICDistributor_SGIR_TargetFilterList(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_TargetFilterList_Pos)) & GICDistributor_SGIR_TargetFilterList_Msk)

#define	GICDistributor_IROUTER_Aff0_Pos 0UL

#define	GICDistributor_IROUTER_Aff0_Msk (0xFFUL /<< GICDistributor_IROUTER_Aff0_Pos/)

#define	GICDistributor_IROUTER_Aff0(x) (((uint64_t)(((uint64_t)(x)) /<< GICDistributor_IROUTER_Aff0_Pos/)) & GICDistributor_IROUTER_Aff0_Msk)

#define	GICDistributor_IROUTER_Aff1_Pos 8UL

#define	GICDistributor_IROUTER_Aff1_Msk (0xFFUL << GICDistributor_IROUTER_Aff1_Pos)

#define	GICDistributor_IROUTER_Aff1(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff1_Pos)) & GICDistributor_IROUTER_Aff1_Msk)

#define	GICDistributor_IROUTER_Aff2_Pos 16UL

#define	GICDistributor_IROUTER_Aff2_Msk (0xFFUL << GICDistributor_IROUTER_Aff2_Pos)

#define	GICDistributor_IROUTER_Aff2(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff2_Pos)) & GICDistributor_IROUTER_Aff2_Msk)

#define	GICDistributor_IROUTER_IRM_Pos 31UL

#define	GICDistributor_IROUTER_IRM_Msk (0xFFUL << GICDistributor_IROUTER_IRM_Pos)

#define	GICDistributor_IROUTER_IRM(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_IRM_Pos)) & GICDistributor_IROUTER_IRM_Msk)

#define	GICDistributor_IROUTER_Aff3_Pos 32UL

#define	GICDistributor_IROUTER_Aff3_Msk (0xFFUL << GICDistributor_IROUTER_Aff3_Pos)

#define	GICDistributor_IROUTER_Aff3(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff3_Pos)) & GICDistributor_IROUTER_Aff3_Msk)

#define	GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE )
	GIC Interface register set access pointer.

#define	GICInterface_CTLR_Enable_Pos 0U

#define	GICInterface_CTLR_Enable_Msk (0x1U /<< GICInterface_CTLR_Enable_Pos/)

#define	GICInterface_CTLR_Enable(x) (((uint32_t)(((uint32_t)(x)) /<< GICInterface_CTLR_Enable_Pos/)) & GICInterface_CTLR_Enable_Msk)

#define	GICInterface_PMR_Priority_Pos 0U

#define	GICInterface_PMR_Priority_Msk (0xFFU /<< GICInterface_PMR_Priority_Pos/)

#define	GICInterface_PMR_Priority(x) (((uint32_t)(((uint32_t)(x)) /<< GICInterface_PMR_Priority_Pos/)) & GICInterface_PMR_Priority_Msk)

#define	GICInterface_BPR_Binary_Point_Pos 0U

#define	GICInterface_BPR_Binary_Point_Msk (0x7U /<< GICInterface_BPR_Binary_Point_Pos/)

#define	GICInterface_BPR_Binary_Point(x) (((uint32_t)(((uint32_t)(x)) /<< GICInterface_BPR_Binary_Point_Pos/)) & GICInterface_BPR_Binary_Point_Msk)

#define	GICInterface_IAR_INTID_Pos 0U

#define	GICInterface_IAR_INTID_Msk (0xFFFFFFU /<< GICInterface_IAR_INTID_Pos/)

#define	GICInterface_IAR_INTID(x) (((uint32_t)(((uint32_t)(x)) /<< GICInterface_IAR_INTID_Pos/)) & GICInterface_IAR_INTID_Msk)

#define	GICInterface_EOIR_INTID_Pos 0U

#define	GICInterface_EOIR_INTID_Msk (0xFFFFFFU /<< GICInterface_EOIR_INTID_Pos/)

#define	GICInterface_EOIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /<< GICInterface_EOIR_INTID_Pos/)) & GICInterface_EOIR_INTID_Msk)

#define	GICInterface_RPR_INTID_Pos 0U

#define	GICInterface_RPR_INTID_Msk (0xFFU /<< GICInterface_RPR_INTID_Pos/)

#define	GICInterface_RPR_INTID(x) (((uint32_t)(((uint32_t)(x)) /<< GICInterface_RPR_INTID_Pos/)) & GICInterface_RPR_INTID_Msk)

#define	GICInterface_HPPIR_INTID_Pos 0U

#define	GICInterface_HPPIR_INTID_Msk (0xFFFFFFU /<< GICInterface_HPPIR_INTID_Pos/)

#define	GICInterface_HPPIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /<< GICInterface_HPPIR_INTID_Pos/)) & GICInterface_HPPIR_INTID_Msk)

#define	GICInterface_ABPR_Binary_Point_Pos 0U

#define	GICInterface_ABPR_Binary_Point_Msk (0x7U /<< GICInterface_ABPR_Binary_Point_Pos/)

#define	GICInterface_ABPR_Binary_Point(x) (((uint32_t)(((uint32_t)(x)) /<< GICInterface_ABPR_Binary_Point_Pos/)) & GICInterface_ABPR_Binary_Point_Msk)

#define	GICInterface_AIAR_INTID_Pos 0U

#define	GICInterface_AIAR_INTID_Msk (0xFFFFFFU /<< GICInterface_AIAR_INTID_Pos/)

#define	GICInterface_AIAR_INTID(x) (((uint32_t)(((uint32_t)(x)) /<< GICInterface_AIAR_INTID_Pos/)) & GICInterface_AIAR_INTID_Msk)

#define	GICInterface_AEOIR_INTID_Pos 0U

#define	GICInterface_AEOIR_INTID_Msk (0xFFFFFFU /<< GICInterface_AEOIR_INTID_Pos/)

#define	GICInterface_AEOIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /<< GICInterface_AEOIR_INTID_Pos/)) & GICInterface_AEOIR_INTID_Msk)

#define	GICInterface_AHPPIR_INTID_Pos 0U

#define	GICInterface_AHPPIR_INTID_Msk (0xFFFFFFU /<< GICInterface_AHPPIR_INTID_Pos/)

#define	GICInterface_AHPPIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /<< GICInterface_AHPPIR_INTID_Pos/)) & GICInterface_AHPPIR_INTID_Msk)

#define	GICInterface_STATUSR_RRD_Pos 0U

#define	GICInterface_STATUSR_RRD_Msk (0x1U /<< GICInterface_STATUSR_RRD_Pos/)

#define	GICInterface_STATUSR_RRD(x) (((uint32_t)(((uint32_t)(x)) /<< GICInterface_STATUSR_RRD_Pos/)) & GICInterface_STATUSR_RRD_Msk)

#define	GICInterface_STATUSR_WRD_Pos 1U

#define	GICInterface_STATUSR_WRD_Msk (0x1U << GICInterface_STATUSR_WRD_Pos)

#define	GICInterface_STATUSR_WRD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_WRD_Pos)) & GICInterface_STATUSR_WRD_Msk)

#define	GICInterface_STATUSR_RWOD_Pos 2U

#define	GICInterface_STATUSR_RWOD_Msk (0x1U << GICInterface_STATUSR_RWOD_Pos)

#define	GICInterface_STATUSR_RWOD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_RWOD_Pos)) & GICInterface_STATUSR_RWOD_Msk)

#define	GICInterface_STATUSR_WROD_Pos 3U

#define	GICInterface_STATUSR_WROD_Msk (0x1U << GICInterface_STATUSR_WROD_Pos)

#define	GICInterface_STATUSR_WROD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_WROD_Pos)) & GICInterface_STATUSR_WROD_Msk)

#define	GICInterface_STATUSR_ASV_Pos 4U

#define	GICInterface_STATUSR_ASV_Msk (0x1U << GICInterface_STATUSR_ASV_Pos)

#define	GICInterface_STATUSR_ASV(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_ASV_Pos)) & GICInterface_STATUSR_ASV_Msk)

#define	GICInterface_IIDR_Implementer_Pos 0U

#define	GICInterface_IIDR_Implementer_Msk (0xFFFU /<< GICInterface_IIDR_Implementer_Pos/)

#define	GICInterface_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) /<< GICInterface_IIDR_Implementer_Pos/)) & GICInterface_IIDR_Implementer_Msk)

#define	GICInterface_IIDR_Revision_Pos 12U

#define	GICInterface_IIDR_Revision_Msk (0xFU << GICInterface_IIDR_Revision_Pos)

#define	GICInterface_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_Revision_Pos)) & GICInterface_IIDR_Revision_Msk)

#define	GICInterface_IIDR_Arch_version_Pos 16U

#define	GICInterface_IIDR_Arch_version_Msk (0xFU << GICInterface_IIDR_Arch_version_Pos)

#define	GICInterface_IIDR_Arch_version(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_Arch_version_Pos)) & GICInterface_IIDR_Arch_version_Msk)

#define	GICInterface_IIDR_ProductID_Pos 20U

#define	GICInterface_IIDR_ProductID_Msk (0xFFFU << GICInterface_IIDR_ProductID_Pos)

#define	GICInterface_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_ProductID_Pos)) & GICInterface_IIDR_ProductID_Msk)

#define	GICInterface_DIR_INTID_Pos 0U

#define	GICInterface_DIR_INTID_Msk (0xFFFFFFU /<< GICInterface_DIR_INTID_Pos/)

#define	GICInterface_DIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /<< GICInterface_DIR_INTID_Pos/)) & GICInterface_DIR_INTID_Msk)

#define	PTIM ((Timer_Type *) TIMER_BASE )
	Timer register struct.

#define	PTIM_CONTROL_Enable_Pos 0U

#define	PTIM_CONTROL_Enable_Msk (0x1U /<< PTIM_CONTROL_Enable_Pos/)

#define	PTIM_CONTROL_Enable(x) (((uint32_t)(((uint32_t)(x)) /<< PTIM_CONTROL_Enable_Pos/)) & PTIM_CONTROL_Enable_Msk)

#define	PTIM_CONTROL_AutoReload_Pos 1U

#define	PTIM_CONTROL_AutoReload_Msk (0x1U << PTIM_CONTROL_AutoReload_Pos)

#define	PTIM_CONTROL_AutoReload(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_AutoReload_Pos)) & PTIM_CONTROL_AutoReload_Msk)

#define	PTIM_CONTROL_IRQenable_Pos 2U

#define	PTIM_CONTROL_IRQenable_Msk (0x1U << PTIM_CONTROL_IRQenable_Pos)

#define	PTIM_CONTROL_IRQenable(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_IRQenable_Pos)) & PTIM_CONTROL_IRQenable_Msk)

#define	PTIM_CONTROL_Prescaler_Pos 8U

#define	PTIM_CONTROL_Prescaler_Msk (0xFFU << PTIM_CONTROL_Prescaler_Pos)

#define	PTIM_CONTROL_Prescaler(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_Prescaler_Pos)) & PTIM_CONTROL_Prescaler_Msk)

#define	PTIM_WCONTROL_Enable_Pos 0U

#define	PTIM_WCONTROL_Enable_Msk (0x1U /<< PTIM_WCONTROL_Enable_Pos/)

#define	PTIM_WCONTROL_Enable(x) (((uint32_t)(((uint32_t)(x)) /<< PTIM_WCONTROL_Enable_Pos/)) & PTIM_WCONTROL_Enable_Msk)

#define	PTIM_WCONTROL_AutoReload_Pos 1U

#define	PTIM_WCONTROL_AutoReload_Msk (0x1U << PTIM_WCONTROL_AutoReload_Pos)

#define	PTIM_WCONTROL_AutoReload(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_AutoReload_Pos)) & PTIM_WCONTROL_AutoReload_Msk)

#define	PTIM_WCONTROL_IRQenable_Pos 2U

#define	PTIM_WCONTROL_IRQenable_Msk (0x1U << PTIM_WCONTROL_IRQenable_Pos)

#define	PTIM_WCONTROL_IRQenable(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_IRQenable_Pos)) & PTIM_WCONTROL_IRQenable_Msk)

#define	PTIM_WCONTROL_Mode_Pos 3U

#define	PTIM_WCONTROL_Mode_Msk (0x1U << PTIM_WCONTROL_Mode_Pos)

#define	PTIM_WCONTROL_Mode(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_Mode_Pos)) & PTIM_WCONTROL_Mode_Msk)

#define	PTIM_WCONTROL_Presacler_Pos 8U

#define	PTIM_WCONTROL_Presacler_Msk (0xFFU << PTIM_WCONTROL_Presacler_Pos)

#define	PTIM_WCONTROL_Presacler(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_Presacler_Pos)) & PTIM_WCONTROL_Presacler_Msk)

#define	PTIM_WISR_EventFlag_Pos 0U

#define	PTIM_WISR_EventFlag_Msk (0x1U /<< PTIM_WISR_EventFlag_Pos/)

#define	PTIM_WISR_EventFlag(x) (((uint32_t)(((uint32_t)(x)) /<< PTIM_WISR_EventFlag_Pos/)) & PTIM_WISR_EventFlag_Msk)

#define	PTIM_WRESET_ResetFlag_Pos 0U

#define	PTIM_WRESET_ResetFlag_Msk (0x1U /<< PTIM_WRESET_ResetFlag_Pos/)

#define	PTIM_WRESET_ResetFlag(x) (((uint32_t)(((uint32_t)(x)) /<< PTIM_WRESET_ResetFlag_Pos/)) & PTIM_WRESET_ResetFlag_Msk)

#define	GIC_SetSecurity GIC_SetGroup

#define	GIC_GetSecurity GIC_GetGroup

#define	SECTION_DESCRIPTOR (0x2)

#define	SECTION_MASK (0xFFFFFFFC)

#define	SECTION_TEXCB_MASK (0xFFFF8FF3)

#define	SECTION_B_SHIFT (2)

#define	SECTION_C_SHIFT (3)

#define	SECTION_TEX0_SHIFT (12)

#define	SECTION_TEX1_SHIFT (13)

#define	SECTION_TEX2_SHIFT (14)

#define	SECTION_XN_MASK (0xFFFFFFEF)

#define	SECTION_XN_SHIFT (4)

#define	SECTION_DOMAIN_MASK (0xFFFFFE1F)

#define	SECTION_DOMAIN_SHIFT (5)

#define	SECTION_P_MASK (0xFFFFFDFF)

#define	SECTION_P_SHIFT (9)

#define	SECTION_AP_MASK (0xFFFF73FF)

#define	SECTION_AP_SHIFT (10)

#define	SECTION_AP2_SHIFT (15)

#define	SECTION_S_MASK (0xFFFEFFFF)

#define	SECTION_S_SHIFT (16)

#define	SECTION_NG_MASK (0xFFFDFFFF)

#define	SECTION_NG_SHIFT (17)

#define	SECTION_NS_MASK (0xFFF7FFFF)

#define	SECTION_NS_SHIFT (19)

#define	PAGE_L1_DESCRIPTOR (0x1)

#define	PAGE_L1_MASK (0xFFFFFFFC)

#define	PAGE_L2_4K_DESC (0x2)

#define	PAGE_L2_4K_MASK (0xFFFFFFFD)

#define	PAGE_L2_64K_DESC (0x1)

#define	PAGE_L2_64K_MASK (0xFFFFFFFC)

#define	PAGE_4K_TEXCB_MASK (0xFFFFFE33)

#define	PAGE_4K_B_SHIFT (2)

#define	PAGE_4K_C_SHIFT (3)

#define	PAGE_4K_TEX0_SHIFT (6)

#define	PAGE_4K_TEX1_SHIFT (7)

#define	PAGE_4K_TEX2_SHIFT (8)

#define	PAGE_64K_TEXCB_MASK (0xFFFF8FF3)

#define	PAGE_64K_B_SHIFT (2)

#define	PAGE_64K_C_SHIFT (3)

#define	PAGE_64K_TEX0_SHIFT (12)

#define	PAGE_64K_TEX1_SHIFT (13)

#define	PAGE_64K_TEX2_SHIFT (14)

#define	PAGE_TEXCB_MASK (0xFFFF8FF3)

#define	PAGE_B_SHIFT (2)

#define	PAGE_C_SHIFT (3)

#define	PAGE_TEX_SHIFT (12)

#define	PAGE_XN_4K_MASK (0xFFFFFFFE)

#define	PAGE_XN_4K_SHIFT (0)

#define	PAGE_XN_64K_MASK (0xFFFF7FFF)

#define	PAGE_XN_64K_SHIFT (15)

#define	PAGE_DOMAIN_MASK (0xFFFFFE1F)

#define	PAGE_DOMAIN_SHIFT (5)

#define	PAGE_P_MASK (0xFFFFFDFF)

#define	PAGE_P_SHIFT (9)

#define	PAGE_AP_MASK (0xFFFFFDCF)

#define	PAGE_AP_SHIFT (4)

#define	PAGE_AP2_SHIFT (9)

#define	PAGE_S_MASK (0xFFFFFBFF)

#define	PAGE_S_SHIFT (10)

#define	PAGE_NG_MASK (0xFFFFF7FF)

#define	PAGE_NG_SHIFT (11)

#define	PAGE_NS_MASK (0xFFFFFFF7)

#define	PAGE_NS_SHIFT (3)

#define	OFFSET_1M (0x00100000)

#define	OFFSET_64K (0x00010000)

#define	OFFSET_4K (0x00001000)

#define	DESCRIPTOR_FAULT (0x00000000)

#define	section_normal(descriptor_l1, region)

#define	section_normal_nc(descriptor_l1, region)

#define	section_normal_cod(descriptor_l1, region)

#define	section_normal_ro(descriptor_l1, region)

#define	section_normal_rw(descriptor_l1, region)

#define	section_so(descriptor_l1, region)

#define	section_device_ro(descriptor_l1, region)

#define	section_device_rw(descriptor_l1, region)

#define	page4k_device_rw(descriptor_l1, descriptor_l2, region)

#define	page64k_device_rw(descriptor_l1, descriptor_l2, region)

Enumerations
enum	mmu_region_size_Type { SECTION , PAGE_4k , PAGE_64k }

enum	mmu_memory_Type { NORMAL , DEVICE , SHARED_DEVICE , NON_SHARED_DEVICE , STRONGLY_ORDERED }

enum	mmu_cacheability_Type { NON_CACHEABLE , WB_WA , WT , WB_NO_WA }

enum	mmu_ecc_check_Type { ECC_DISABLED , ECC_ENABLED }

enum	mmu_execute_Type { EXECUTE , NON_EXECUTE }

enum	mmu_global_Type { GLOBAL , NON_GLOBAL }

enum	mmu_shared_Type { NON_SHARED , SHARED }

enum	mmu_secure_Type { SECURE , NON_SECURE }

enum	mmu_access_Type { NO_ACCESS , RW , READ }

Functions
__STATIC_FORCEINLINE void	L1C_EnableCaches (void)
	Enable Caches by setting I and C bits in SCTLR register.

__STATIC_FORCEINLINE void	L1C_DisableCaches (void)
	Disable Caches by clearing I and C bits in SCTLR register.

__STATIC_FORCEINLINE void	L1C_EnableBTAC (void)
	Enable Branch Prediction by setting Z bit in SCTLR register.

__STATIC_FORCEINLINE void	L1C_DisableBTAC (void)
	Disable Branch Prediction by clearing Z bit in SCTLR register.

__STATIC_FORCEINLINE void	L1C_InvalidateBTAC (void)
	Invalidate entire branch predictor array.

__STATIC_FORCEINLINE void	L1C_InvalidateICacheMVA (void *va)
	Clean instruction cache line by address.

__STATIC_FORCEINLINE void	L1C_InvalidateICacheAll (void)
	Invalidate the whole instruction cache.

__STATIC_FORCEINLINE void	L1C_CleanDCacheMVA (void *va)
	Clean data cache line by address.

__STATIC_FORCEINLINE void	L1C_InvalidateDCacheMVA (void *va)
	Invalidate data cache line by address.

__STATIC_FORCEINLINE void	L1C_CleanInvalidateDCacheMVA (void *va)
	Clean and Invalidate data cache by address.

__STATIC_FORCEINLINE uint8_t	__log2_up (uint32_t n)
	Calculate log2 rounded up.

__STATIC_FORCEINLINE void	__L1C_MaintainDCacheSetWay (uint32_t level, uint32_t maint)
	Apply cache maintenance to given cache level.

__STATIC_FORCEINLINE void	L1C_CleanInvalidateCache (uint32_t op)
	Clean and Invalidate the entire data or unified cache.

__STATIC_FORCEINLINE void	L1C_InvalidateDCacheAll (void)
	Invalidate the whole data cache.

__STATIC_FORCEINLINE void	L1C_CleanDCacheAll (void)
	Clean the whole data cache.

__STATIC_FORCEINLINE void	L1C_CleanInvalidateDCacheAll (void)
	Clean and invalidate the whole data cache.

__STATIC_INLINE void	L2C_Sync (void)
	Cache Sync operation by writing CACHE_SYNC register.

__STATIC_INLINE int	L2C_GetID (void)
	Read cache controller cache ID from CACHE_ID register.

__STATIC_INLINE int	L2C_GetType (void)
	Read cache controller cache type from CACHE_TYPE register.

__STATIC_INLINE void	L2C_InvAllByWay (void)
	Invalidate all cache by way.

__STATIC_INLINE void	L2C_CleanInvAllByWay (void)
	Clean and Invalidate all cache by way.

__STATIC_INLINE void	L2C_Enable (void)
	Enable Level 2 Cache.

__STATIC_INLINE void	L2C_Disable (void)
	Disable Level 2 Cache.

__STATIC_INLINE void	L2C_InvPa (void *pa)
	Invalidate cache by physical address.

__STATIC_INLINE void	L2C_CleanPa (void *pa)
	Clean cache by physical address.

__STATIC_INLINE void	L2C_CleanInvPa (void *pa)
	Clean and invalidate cache by physical address.

__STATIC_INLINE void	GIC_EnableDistributor (void)
	Enable the interrupt distributor using the GIC's CTLR register.

__STATIC_INLINE void	GIC_DisableDistributor (void)
	Disable the interrupt distributor using the GIC's CTLR register.

__STATIC_INLINE uint32_t	GIC_DistributorInfo (void)
	Read the GIC's TYPER register.

__STATIC_INLINE uint32_t	GIC_DistributorImplementer (void)
	Reads the GIC's IIDR register.

__STATIC_INLINE void	GIC_SetTarget (IRQn_Type IRQn, uint32_t cpu_target)
	Sets the GIC's ITARGETSR register for the given interrupt.

__STATIC_INLINE uint32_t	GIC_GetTarget (IRQn_Type IRQn)
	Read the GIC's ITARGETSR register.

__STATIC_INLINE void	GIC_EnableInterface (void)
	Enable the CPU's interrupt interface.

__STATIC_INLINE void	GIC_DisableInterface (void)
	Disable the CPU's interrupt interface.

__STATIC_INLINE IRQn_Type	GIC_AcknowledgePending (void)
	Read the CPU's IAR register.

__STATIC_INLINE void	GIC_EndInterrupt (IRQn_Type IRQn)
	Writes the given interrupt number to the CPU's EOIR register.

__STATIC_INLINE void	GIC_EnableIRQ (IRQn_Type IRQn)
	Enables the given interrupt using GIC's ISENABLER register.

__STATIC_INLINE uint32_t	GIC_GetEnableIRQ (IRQn_Type IRQn)
	Get interrupt enable status using GIC's ISENABLER register.

__STATIC_INLINE void	GIC_DisableIRQ (IRQn_Type IRQn)
	Disables the given interrupt using GIC's ICENABLER register.

__STATIC_INLINE uint32_t	GIC_GetPendingIRQ (IRQn_Type IRQn)
	Get interrupt pending status from GIC's ISPENDR register.

__STATIC_INLINE void	GIC_SetPendingIRQ (IRQn_Type IRQn)
	Sets the given interrupt as pending using GIC's ISPENDR register.

__STATIC_INLINE void	GIC_ClearPendingIRQ (IRQn_Type IRQn)
	Clears the given interrupt from being pending using GIC's ICPENDR register.

__STATIC_INLINE void	GIC_SetConfiguration (IRQn_Type IRQn, uint32_t int_config)
	Sets the interrupt configuration using GIC's ICFGR register.

__STATIC_INLINE uint32_t	GIC_GetConfiguration (IRQn_Type IRQn)
	Get the interrupt configuration from the GIC's ICFGR register.

__STATIC_INLINE void	GIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
	Set the priority for the given interrupt in the GIC's IPRIORITYR register.

__STATIC_INLINE uint32_t	GIC_GetPriority (IRQn_Type IRQn)
	Read the current interrupt priority from GIC's IPRIORITYR register.

__STATIC_INLINE void	GIC_SetInterfacePriorityMask (uint32_t priority)
	Set the interrupt priority mask using CPU's PMR register.

__STATIC_INLINE uint32_t	GIC_GetInterfacePriorityMask (void)
	Read the current interrupt priority mask from CPU's PMR register.

__STATIC_INLINE void	GIC_SetBinaryPoint (uint32_t binary_point)
	Configures the group priority and subpriority split point using CPU's BPR register.

__STATIC_INLINE uint32_t	GIC_GetBinaryPoint (void)
	Read the current group priority and subpriority split point from CPU's BPR register.

__STATIC_INLINE uint32_t	GIC_GetIRQStatus (IRQn_Type IRQn)
	Get the status for a given interrupt.

__STATIC_INLINE void	GIC_SendSGI (IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
	Generate a software interrupt using GIC's SGIR register.

__STATIC_INLINE uint32_t	GIC_GetHighPendingIRQ (void)
	Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.

__STATIC_INLINE uint32_t	GIC_GetInterfaceId (void)
	Provides information about the implementer and revision of the CPU interface.

__STATIC_INLINE void	GIC_SetGroup (IRQn_Type IRQn, uint32_t group)
	Set the interrupt group from the GIC's IGROUPR register.

__STATIC_INLINE uint32_t	GIC_GetGroup (IRQn_Type IRQn)
	Get the interrupt group from the GIC's IGROUPR register.

__STATIC_INLINE void	GIC_DistInit (void)
	Initialize the interrupt distributor.

__STATIC_INLINE void	GIC_CPUInterfaceInit (void)
	Initialize the CPU's interrupt interface.

__STATIC_INLINE void	GIC_Enable (void)
	Initialize and enable the GIC.

__STATIC_INLINE void	PL1_SetCounterFrequency (uint32_t value)
	Configures the frequency the timer shall run at.

__STATIC_INLINE void	PL1_SetLoadValue (uint32_t value)
	Sets the reset value of the timer.

__STATIC_INLINE uint32_t	PL1_GetCurrentValue (void)
	Get the current counter value.

__STATIC_INLINE uint64_t	PL1_GetCurrentPhysicalValue (void)
	Get the current physical counter value.

__STATIC_INLINE void	PL1_SetPhysicalCompareValue (uint64_t value)
	Set the physical compare value.

__STATIC_INLINE uint64_t	PL1_GetPhysicalCompareValue (void)
	Get the physical compare value.

__STATIC_INLINE void	PL1_SetControl (uint32_t value)
	Configure the timer by setting the control value.

__STATIC_INLINE uint32_t	PL1_GetControl (void)
	Get the control value.

__STATIC_INLINE void	VL1_SetCurrentTimerValue (uint32_t value)
	Virtual Timer Control register.

__STATIC_INLINE uint32_t	VL1_GetCurrentTimerValue (void)
	Get the current virtual timer value.

__STATIC_INLINE uint64_t	VL1_GetCurrentCountValue (void)
	Get the current virtual count value.

__STATIC_INLINE void	VL1_SetTimerCompareValue (uint64_t value)
	Set the virtual timer compare value.

__STATIC_INLINE uint64_t	VL1_GetTimerCompareValue (void)
	Get the virtual timer compare value.

__STATIC_INLINE void	VL1_SetControl (uint32_t value)
	Configure the virtual timer by setting the control value.

__STATIC_INLINE uint32_t	VL1_GetControl (void)
	Get the virtual timer control value.

__STATIC_INLINE void	PTIM_SetLoadValue (uint32_t value)
	Set the load value to timers LOAD register.

__STATIC_INLINE uint32_t	PTIM_GetLoadValue (void)
	Get the load value from timers LOAD register.

__STATIC_INLINE void	PTIM_SetCurrentValue (uint32_t value)
	Set current counter value from its COUNTER register.

__STATIC_INLINE uint32_t	PTIM_GetCurrentValue (void)
	Get current counter value from timers COUNTER register.

__STATIC_INLINE void	PTIM_SetControl (uint32_t value)
	Configure the timer using its CONTROL register.

__STATIC_INLINE uint32_t	PTIM_GetControl (void)

__STATIC_INLINE uint32_t	PTIM_GetEventFlag (void)

__STATIC_INLINE void	PTIM_ClearEventFlag (void)

__STATIC_INLINE int	MMU_XNSection (uint32_t *descriptor_l1, mmu_execute_Type xn)
	Set section execution-never attribute.

__STATIC_INLINE int	MMU_DomainSection (uint32_t *descriptor_l1, uint8_t domain)
	Set section domain.

__STATIC_INLINE int	MMU_PSection (uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
	Set section parity check.

__STATIC_INLINE int	MMU_APSection (uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
	Set section access privileges.

__STATIC_INLINE int	MMU_SharedSection (uint32_t *descriptor_l1, mmu_shared_Type s_bit)
	Set section shareability.

__STATIC_INLINE int	MMU_GlobalSection (uint32_t *descriptor_l1, mmu_global_Type g_bit)
	Set section Global attribute.

__STATIC_INLINE int	MMU_SecureSection (uint32_t *descriptor_l1, mmu_secure_Type s_bit)
	Set section Security attribute.

__STATIC_INLINE int	MMU_XNPage (uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
	Set 4k/64k page execution-never attribute.

__STATIC_INLINE int	MMU_DomainPage (uint32_t *descriptor_l1, uint8_t domain)
	Set 4k/64k page domain.

__STATIC_INLINE int	MMU_PPage (uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
	Set 4k/64k page parity check.

__STATIC_INLINE int	MMU_APPage (uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
	Set 4k/64k page access privileges.

__STATIC_INLINE int	MMU_SharedPage (uint32_t *descriptor_l2, mmu_shared_Type s_bit)
	Set 4k/64k page shareability.

__STATIC_INLINE int	MMU_GlobalPage (uint32_t *descriptor_l2, mmu_global_Type g_bit)
	Set 4k/64k page Global attribute.

__STATIC_INLINE int	MMU_SecurePage (uint32_t *descriptor_l1, mmu_secure_Type s_bit)
	Set 4k/64k page Security attribute.

__STATIC_INLINE int	MMU_MemorySection (uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
	Set Section memory attributes.

__STATIC_INLINE int	MMU_MemoryPage (uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
	Set 4k/64k page memory attributes.

__STATIC_INLINE int	MMU_GetSectionDescriptor (uint32_t *descriptor, mmu_region_attributes_Type reg)
	Create a L1 section descriptor.

__STATIC_INLINE int	MMU_GetPageDescriptor (uint32_t descriptor, uint32_t descriptor2, mmu_region_attributes_Type reg)
	Create a L1 and L2 4k/64k page descriptor.

__STATIC_INLINE void	MMU_TTSection (uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
	Create a 1MB Section.

__STATIC_INLINE void	MMU_TTPage4k (uint32_t ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t ttb_l2, uint32_t descriptor_l2)
	Create a 4k page entry.

__STATIC_INLINE void	MMU_TTPage64k (uint32_t ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t ttb_l2, uint32_t descriptor_l2)
	Create a 64k page entry.

__STATIC_INLINE void	MMU_Enable (void)
	Enable MMU.

__STATIC_INLINE void	MMU_Disable (void)
	Disable MMU.

__STATIC_INLINE void	MMU_InvalidateTLB (void)
	Invalidate entire unified TLB.

Macro Definition Documentation

◆ __CORE_CA_H_DEPENDANT

#define __CORE_CA_H_DEPENDANT

◆ __FPU_PRESENT

#define __FPU_PRESENT 0U

◆ __FPU_USED

#define __FPU_USED 0U

◆ __GIC_PRESENT

#define __GIC_PRESENT 1U

◆ __I

#define __I volatile

Defines 'read only' permissions.

◆ __IM

#define __IM volatile const

Defines 'read only' structure member permissions.

◆ __IO

#define __IO volatile

Defines 'read / write' permissions.

◆ __IOM

#define __IOM volatile

Defines 'read / write' structure member permissions.

◆ __O

#define __O volatile

Defines 'write only' permissions.

◆ __OM

#define __OM volatile

Defines 'write only' structure member permissions.

◆ __TIM_PRESENT

#define __TIM_PRESENT 1U

◆ _FLD2VAL

#define _FLD2VAL	(	field,
		value
	)	(((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of register. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted bit field value.

◆ _VAL2FLD

#define _VAL2FLD	(	field,
		value
	)	(((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of the bit field. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted value.

◆ DESCRIPTOR_FAULT

#define DESCRIPTOR_FAULT (0x00000000)

◆ GIC_GetSecurity

#define GIC_GetSecurity GIC_GetGroup

◆ GIC_SetSecurity

#define GIC_SetSecurity GIC_SetGroup

◆ GICDistributor_CLRSPI_NSR_INTID

#define GICDistributor_CLRSPI_NSR_INTID ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CLRSPI_NSR_INTID_Pos*/)) & GICDistributor_CLRSPI_NSR_INTID_Msk)

◆ GICDistributor_CLRSPI_NSR_INTID_Msk

#define GICDistributor_CLRSPI_NSR_INTID_Msk (0x3FFU /*<< GICDistributor_CLRSPI_NSR_INTID_Pos*/)

GICDistributor CLRSPI_NSR: INTID Mask

◆ GICDistributor_CLRSPI_NSR_INTID_Pos

#define GICDistributor_CLRSPI_NSR_INTID_Pos 0U

GICDistributor CLRSPI_NSR: INTID Position

◆ GICDistributor_CLRSPI_SR_INTID

#define GICDistributor_CLRSPI_SR_INTID ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CLRSPI_SR_INTID_Pos*/)) & GICDistributor_CLRSPI_SR_INTID_Msk)

◆ GICDistributor_CLRSPI_SR_INTID_Msk

#define GICDistributor_CLRSPI_SR_INTID_Msk (0x3FFU /*<< GICDistributor_CLRSPI_SR_INTID_Pos*/)

GICDistributor CLRSPI_SR: INTID Mask

◆ GICDistributor_CLRSPI_SR_INTID_Pos

#define GICDistributor_CLRSPI_SR_INTID_Pos 0U

GICDistributor CLRSPI_SR: INTID Position

◆ GICDistributor_CTLR_ARE

#define GICDistributor_CTLR_ARE ( x ) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_ARE_Pos)) & GICDistributor_CTLR_ARE_Msk)

◆ GICDistributor_CTLR_ARE_Msk

#define GICDistributor_CTLR_ARE_Msk (0x1U << GICDistributor_CTLR_ARE_Pos)

GICDistributor CTLR: ARE Mask

◆ GICDistributor_CTLR_ARE_Pos

#define GICDistributor_CTLR_ARE_Pos 4U

GICDistributor CTLR: ARE Position

◆ GICDistributor_CTLR_DC

#define GICDistributor_CTLR_DC ( x ) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_DC_Pos)) & GICDistributor_CTLR_DC_Msk)

◆ GICDistributor_CTLR_DC_Msk

#define GICDistributor_CTLR_DC_Msk (0x1U << GICDistributor_CTLR_DC_Pos)

GICDistributor CTLR: DC Mask

◆ GICDistributor_CTLR_DC_Pos

#define GICDistributor_CTLR_DC_Pos 6U

GICDistributor CTLR: DC Position

◆ GICDistributor_CTLR_EINWF

#define GICDistributor_CTLR_EINWF ( x ) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_EINWF_Pos)) & GICDistributor_CTLR_EINWF_Msk)

◆ GICDistributor_CTLR_EINWF_Msk

#define GICDistributor_CTLR_EINWF_Msk (0x1U << GICDistributor_CTLR_EINWF_Pos)

GICDistributor CTLR: EINWF Mask

◆ GICDistributor_CTLR_EINWF_Pos

#define GICDistributor_CTLR_EINWF_Pos 7U

GICDistributor CTLR: EINWF Position

◆ GICDistributor_CTLR_EnableGrp0

#define GICDistributor_CTLR_EnableGrp0 ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CTLR_EnableGrp0_Pos*/)) & GICDistributor_CTLR_EnableGrp0_Msk)

◆ GICDistributor_CTLR_EnableGrp0_Msk

#define GICDistributor_CTLR_EnableGrp0_Msk (0x1U /*<< GICDistributor_CTLR_EnableGrp0_Pos*/)

GICDistributor CTLR: EnableGrp0 Mask

◆ GICDistributor_CTLR_EnableGrp0_Pos

#define GICDistributor_CTLR_EnableGrp0_Pos 0U

GICDistributor CTLR: EnableGrp0 Position

◆ GICDistributor_CTLR_EnableGrp1

#define GICDistributor_CTLR_EnableGrp1 ( x ) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_EnableGrp1_Pos)) & GICDistributor_CTLR_EnableGrp1_Msk)

◆ GICDistributor_CTLR_EnableGrp1_Msk

#define GICDistributor_CTLR_EnableGrp1_Msk (0x1U << GICDistributor_CTLR_EnableGrp1_Pos)

GICDistributor CTLR: EnableGrp1 Mask

◆ GICDistributor_CTLR_EnableGrp1_Pos

#define GICDistributor_CTLR_EnableGrp1_Pos 1U

GICDistributor CTLR: EnableGrp1 Position

◆ GICDistributor_CTLR_RWP

#define GICDistributor_CTLR_RWP ( x ) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_RWP_Pos)) & GICDistributor_CTLR_RWP_Msk)

◆ GICDistributor_CTLR_RWP_Msk

#define GICDistributor_CTLR_RWP_Msk (0x1U << GICDistributor_CTLR_RWP_Pos)

GICDistributor CTLR: RWP Mask

◆ GICDistributor_CTLR_RWP_Pos

#define GICDistributor_CTLR_RWP_Pos 31U

GICDistributor CTLR: RWP Position

◆ GICDistributor_IIDR_Implementer

#define GICDistributor_IIDR_Implementer ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_IIDR_Implementer_Pos*/)) & GICDistributor_IIDR_Implementer_Msk)

◆ GICDistributor_IIDR_Implementer_Msk

#define GICDistributor_IIDR_Implementer_Msk (0xFFFU /*<< GICDistributor_IIDR_Implementer_Pos*/)

GICDistributor IIDR: Implementer Mask

◆ GICDistributor_IIDR_Implementer_Pos

#define GICDistributor_IIDR_Implementer_Pos 0U

GICDistributor IIDR: Implementer Position

◆ GICDistributor_IIDR_ProductID

#define GICDistributor_IIDR_ProductID ( x ) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_ProductID_Pos)) & GICDistributor_IIDR_ProductID_Msk)

◆ GICDistributor_IIDR_ProductID_Msk

#define GICDistributor_IIDR_ProductID_Msk (0xFFU << GICDistributor_IIDR_ProductID_Pos)

GICDistributor IIDR: ProductID Mask

◆ GICDistributor_IIDR_ProductID_Pos

#define GICDistributor_IIDR_ProductID_Pos 24U

GICDistributor IIDR: ProductID Position

◆ GICDistributor_IIDR_Revision

#define GICDistributor_IIDR_Revision ( x ) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_Revision_Pos)) & GICDistributor_IIDR_Revision_Msk)

◆ GICDistributor_IIDR_Revision_Msk

#define GICDistributor_IIDR_Revision_Msk (0xFU << GICDistributor_IIDR_Revision_Pos)

GICDistributor IIDR: Revision Mask

◆ GICDistributor_IIDR_Revision_Pos

#define GICDistributor_IIDR_Revision_Pos 12U

GICDistributor IIDR: Revision Position

◆ GICDistributor_IIDR_Variant

#define GICDistributor_IIDR_Variant ( x ) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_Variant_Pos)) & GICDistributor_IIDR_Variant_Msk)

◆ GICDistributor_IIDR_Variant_Msk

#define GICDistributor_IIDR_Variant_Msk (0xFU << GICDistributor_IIDR_Variant_Pos)

GICDistributor IIDR: Variant Mask

◆ GICDistributor_IIDR_Variant_Pos

#define GICDistributor_IIDR_Variant_Pos 16U

GICDistributor IIDR: Variant Position

◆ GICDistributor_IROUTER_Aff0

#define GICDistributor_IROUTER_Aff0 ( x ) (((uint64_t)(((uint64_t)(x)) /*<< GICDistributor_IROUTER_Aff0_Pos*/)) & GICDistributor_IROUTER_Aff0_Msk)

◆ GICDistributor_IROUTER_Aff0_Msk

#define GICDistributor_IROUTER_Aff0_Msk (0xFFUL /*<< GICDistributor_IROUTER_Aff0_Pos*/)

GICDistributor IROUTER: Aff0 Mask

◆ GICDistributor_IROUTER_Aff0_Pos

#define GICDistributor_IROUTER_Aff0_Pos 0UL

GICDistributor IROUTER: Aff0 Position

◆ GICDistributor_IROUTER_Aff1

#define GICDistributor_IROUTER_Aff1 ( x ) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff1_Pos)) & GICDistributor_IROUTER_Aff1_Msk)

◆ GICDistributor_IROUTER_Aff1_Msk

#define GICDistributor_IROUTER_Aff1_Msk (0xFFUL << GICDistributor_IROUTER_Aff1_Pos)

GICDistributor IROUTER: Aff1 Mask

◆ GICDistributor_IROUTER_Aff1_Pos

#define GICDistributor_IROUTER_Aff1_Pos 8UL

GICDistributor IROUTER: Aff1 Position

◆ GICDistributor_IROUTER_Aff2

#define GICDistributor_IROUTER_Aff2 ( x ) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff2_Pos)) & GICDistributor_IROUTER_Aff2_Msk)

◆ GICDistributor_IROUTER_Aff2_Msk

#define GICDistributor_IROUTER_Aff2_Msk (0xFFUL << GICDistributor_IROUTER_Aff2_Pos)

GICDistributor IROUTER: Aff2 Mask

◆ GICDistributor_IROUTER_Aff2_Pos

#define GICDistributor_IROUTER_Aff2_Pos 16UL

GICDistributor IROUTER: Aff2 Position

◆ GICDistributor_IROUTER_Aff3

#define GICDistributor_IROUTER_Aff3 ( x ) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff3_Pos)) & GICDistributor_IROUTER_Aff3_Msk)

◆ GICDistributor_IROUTER_Aff3_Msk

#define GICDistributor_IROUTER_Aff3_Msk (0xFFUL << GICDistributor_IROUTER_Aff3_Pos)

GICDistributor IROUTER: Aff3 Mask

◆ GICDistributor_IROUTER_Aff3_Pos

#define GICDistributor_IROUTER_Aff3_Pos 32UL

GICDistributor IROUTER: Aff3 Position

◆ GICDistributor_IROUTER_IRM

#define GICDistributor_IROUTER_IRM ( x ) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_IRM_Pos)) & GICDistributor_IROUTER_IRM_Msk)

◆ GICDistributor_IROUTER_IRM_Msk

#define GICDistributor_IROUTER_IRM_Msk (0xFFUL << GICDistributor_IROUTER_IRM_Pos)

GICDistributor IROUTER: IRM Mask

◆ GICDistributor_IROUTER_IRM_Pos

#define GICDistributor_IROUTER_IRM_Pos 31UL

GICDistributor IROUTER: IRM Position

◆ GICDistributor_ITARGETSR_CPU0

#define GICDistributor_ITARGETSR_CPU0 ( x ) (((uint8_t)(((uint8_t)(x)) /*<< GICDistributor_ITARGETSR_CPU0_Pos*/)) & GICDistributor_ITARGETSR_CPU0_Msk)

◆ GICDistributor_ITARGETSR_CPU0_Msk

#define GICDistributor_ITARGETSR_CPU0_Msk (0x1U /*<< GICDistributor_ITARGETSR_CPU0_Pos*/)

GICDistributor ITARGETSR: CPU0 Mask

◆ GICDistributor_ITARGETSR_CPU0_Pos

#define GICDistributor_ITARGETSR_CPU0_Pos 0U

GICDistributor ITARGETSR: CPU0 Position

◆ GICDistributor_ITARGETSR_CPU1

#define GICDistributor_ITARGETSR_CPU1 ( x ) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU1_Pos)) & GICDistributor_ITARGETSR_CPU1_Msk)

◆ GICDistributor_ITARGETSR_CPU1_Msk

#define GICDistributor_ITARGETSR_CPU1_Msk (0x1U << GICDistributor_ITARGETSR_CPU1_Pos)

GICDistributor ITARGETSR: CPU1 Mask

◆ GICDistributor_ITARGETSR_CPU1_Pos

#define GICDistributor_ITARGETSR_CPU1_Pos 1U

GICDistributor ITARGETSR: CPU1 Position

◆ GICDistributor_ITARGETSR_CPU2

#define GICDistributor_ITARGETSR_CPU2 ( x ) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU2_Pos)) & GICDistributor_ITARGETSR_CPU2_Msk)

◆ GICDistributor_ITARGETSR_CPU2_Msk

#define GICDistributor_ITARGETSR_CPU2_Msk (0x1U << GICDistributor_ITARGETSR_CPU2_Pos)

GICDistributor ITARGETSR: CPU2 Mask

◆ GICDistributor_ITARGETSR_CPU2_Pos

#define GICDistributor_ITARGETSR_CPU2_Pos 2U

GICDistributor ITARGETSR: CPU2 Position

◆ GICDistributor_ITARGETSR_CPU3

#define GICDistributor_ITARGETSR_CPU3 ( x ) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU3_Pos)) & GICDistributor_ITARGETSR_CPU3_Msk)

◆ GICDistributor_ITARGETSR_CPU3_Msk

#define GICDistributor_ITARGETSR_CPU3_Msk (0x1U << GICDistributor_ITARGETSR_CPU3_Pos)

GICDistributor ITARGETSR: CPU3 Mask

◆ GICDistributor_ITARGETSR_CPU3_Pos

#define GICDistributor_ITARGETSR_CPU3_Pos 3U

GICDistributor ITARGETSR: CPU3 Position

◆ GICDistributor_ITARGETSR_CPU4

#define GICDistributor_ITARGETSR_CPU4 ( x ) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU4_Pos)) & GICDistributor_ITARGETSR_CPU4_Msk)

◆ GICDistributor_ITARGETSR_CPU4_Msk

#define GICDistributor_ITARGETSR_CPU4_Msk (0x1U << GICDistributor_ITARGETSR_CPU4_Pos)

GICDistributor ITARGETSR: CPU4 Mask

◆ GICDistributor_ITARGETSR_CPU4_Pos

#define GICDistributor_ITARGETSR_CPU4_Pos 4U

GICDistributor ITARGETSR: CPU4 Position

◆ GICDistributor_ITARGETSR_CPU5

#define GICDistributor_ITARGETSR_CPU5 ( x ) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU5_Pos)) & GICDistributor_ITARGETSR_CPU5_Msk)

◆ GICDistributor_ITARGETSR_CPU5_Msk

#define GICDistributor_ITARGETSR_CPU5_Msk (0x1U << GICDistributor_ITARGETSR_CPU5_Pos)

GICDistributor ITARGETSR: CPU5 Mask

◆ GICDistributor_ITARGETSR_CPU5_Pos

#define GICDistributor_ITARGETSR_CPU5_Pos 5U

GICDistributor ITARGETSR: CPU5 Position

◆ GICDistributor_ITARGETSR_CPU6

#define GICDistributor_ITARGETSR_CPU6 ( x ) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU6_Pos)) & GICDistributor_ITARGETSR_CPU6_Msk)

◆ GICDistributor_ITARGETSR_CPU6_Msk

#define GICDistributor_ITARGETSR_CPU6_Msk (0x1U << GICDistributor_ITARGETSR_CPU6_Pos)

GICDistributor ITARGETSR: CPU6 Mask

◆ GICDistributor_ITARGETSR_CPU6_Pos

#define GICDistributor_ITARGETSR_CPU6_Pos 6U

GICDistributor ITARGETSR: CPU6 Position

◆ GICDistributor_ITARGETSR_CPU7

#define GICDistributor_ITARGETSR_CPU7 ( x ) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU7_Pos)) & GICDistributor_ITARGETSR_CPU7_Msk)

◆ GICDistributor_ITARGETSR_CPU7_Msk

#define GICDistributor_ITARGETSR_CPU7_Msk (0x1U << GICDistributor_ITARGETSR_CPU7_Pos)

GICDistributor ITARGETSR: CPU7 Mask

◆ GICDistributor_ITARGETSR_CPU7_Pos

#define GICDistributor_ITARGETSR_CPU7_Pos 7U

GICDistributor ITARGETSR: CPU7 Position

◆ GICDistributor_SETSPI_NSR_INTID

#define GICDistributor_SETSPI_NSR_INTID ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SETSPI_NSR_INTID_Pos*/)) & GICDistributor_SETSPI_NSR_INTID_Msk)

◆ GICDistributor_SETSPI_NSR_INTID_Msk

#define GICDistributor_SETSPI_NSR_INTID_Msk (0x3FFU /*<< GICDistributor_SETSPI_NSR_INTID_Pos*/)

GICDistributor SETSPI_NSR: INTID Mask

◆ GICDistributor_SETSPI_NSR_INTID_Pos

#define GICDistributor_SETSPI_NSR_INTID_Pos 0U

GICDistributor SETSPI_NSR: INTID Position

◆ GICDistributor_SETSPI_SR_INTID

#define GICDistributor_SETSPI_SR_INTID ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SETSPI_SR_INTID_Pos*/)) & GICDistributor_SETSPI_SR_INTID_Msk)

◆ GICDistributor_SETSPI_SR_INTID_Msk

#define GICDistributor_SETSPI_SR_INTID_Msk (0x3FFU /*<< GICDistributor_SETSPI_SR_INTID_Pos*/)

GICDistributor SETSPI_SR: INTID Mask

◆ GICDistributor_SETSPI_SR_INTID_Pos

#define GICDistributor_SETSPI_SR_INTID_Pos 0U

GICDistributor SETSPI_SR: INTID Position

◆ GICDistributor_SGIR_CPUTargetList

#define GICDistributor_SGIR_CPUTargetList ( x ) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_CPUTargetList_Pos)) & GICDistributor_SGIR_CPUTargetList_Msk)

◆ GICDistributor_SGIR_CPUTargetList_Msk

#define GICDistributor_SGIR_CPUTargetList_Msk (0xFFU << GICDistributor_SGIR_CPUTargetList_Pos)

GICDistributor SGIR: CPUTargetList Mask

◆ GICDistributor_SGIR_CPUTargetList_Pos

#define GICDistributor_SGIR_CPUTargetList_Pos 16U

GICDistributor SGIR: CPUTargetList Position

◆ GICDistributor_SGIR_INTID

#define GICDistributor_SGIR_INTID ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SGIR_INTID_Pos*/)) & GICDistributor_SGIR_INTID_Msk)

◆ GICDistributor_SGIR_INTID_Msk

#define GICDistributor_SGIR_INTID_Msk (0x7U /*<< GICDistributor_SGIR_INTID_Pos*/)

GICDistributor SGIR: INTID Mask

◆ GICDistributor_SGIR_INTID_Pos

#define GICDistributor_SGIR_INTID_Pos 0U

GICDistributor SGIR: INTID Position

◆ GICDistributor_SGIR_NSATT

#define GICDistributor_SGIR_NSATT ( x ) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_NSATT_Pos)) & GICDistributor_SGIR_NSATT_Msk)

◆ GICDistributor_SGIR_NSATT_Msk

#define GICDistributor_SGIR_NSATT_Msk (0x1U << GICDistributor_SGIR_NSATT_Pos)

GICDistributor SGIR: NSATT Mask

◆ GICDistributor_SGIR_NSATT_Pos

#define GICDistributor_SGIR_NSATT_Pos 15U

GICDistributor SGIR: NSATT Position

◆ GICDistributor_SGIR_TargetFilterList

#define GICDistributor_SGIR_TargetFilterList ( x ) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_TargetFilterList_Pos)) & GICDistributor_SGIR_TargetFilterList_Msk)

◆ GICDistributor_SGIR_TargetFilterList_Msk

#define GICDistributor_SGIR_TargetFilterList_Msk (0x3U << GICDistributor_SGIR_TargetFilterList_Pos)

GICDistributor SGIR: TargetFilterList Mask

◆ GICDistributor_SGIR_TargetFilterList_Pos

#define GICDistributor_SGIR_TargetFilterList_Pos 24U

GICDistributor SGIR: TargetFilterList Position

◆ GICDistributor_STATUSR_RRD

#define GICDistributor_STATUSR_RRD ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_STATUSR_RRD_Pos*/)) & GICDistributor_STATUSR_RRD_Msk)

◆ GICDistributor_STATUSR_RRD_Msk

#define GICDistributor_STATUSR_RRD_Msk (0x1U /*<< GICDistributor_STATUSR_RRD_Pos*/)

GICDistributor STATUSR: RRD Mask

◆ GICDistributor_STATUSR_RRD_Pos

#define GICDistributor_STATUSR_RRD_Pos 0U

GICDistributor STATUSR: RRD Position

◆ GICDistributor_STATUSR_RWOD

#define GICDistributor_STATUSR_RWOD ( x ) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_RWOD_Pos)) & GICDistributor_STATUSR_RWOD_Msk)

◆ GICDistributor_STATUSR_RWOD_Msk

#define GICDistributor_STATUSR_RWOD_Msk (0x1U << GICDistributor_STATUSR_RWOD_Pos)

GICDistributor STATUSR: RWOD Mask

◆ GICDistributor_STATUSR_RWOD_Pos

#define GICDistributor_STATUSR_RWOD_Pos 2U

GICDistributor STATUSR: RWOD Position

◆ GICDistributor_STATUSR_WRD

#define GICDistributor_STATUSR_WRD ( x ) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_WRD_Pos)) & GICDistributor_STATUSR_WRD_Msk)

◆ GICDistributor_STATUSR_WRD_Msk

#define GICDistributor_STATUSR_WRD_Msk (0x1U << GICDistributor_STATUSR_WRD_Pos)

GICDistributor STATUSR: WRD Mask

◆ GICDistributor_STATUSR_WRD_Pos

#define GICDistributor_STATUSR_WRD_Pos 1U

GICDistributor STATUSR: WRD Position

◆ GICDistributor_STATUSR_WROD

#define GICDistributor_STATUSR_WROD ( x ) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_WROD_Pos)) & GICDistributor_STATUSR_WROD_Msk)

◆ GICDistributor_STATUSR_WROD_Msk

#define GICDistributor_STATUSR_WROD_Msk (0x1U << GICDistributor_STATUSR_WROD_Pos)

GICDistributor STATUSR: WROD Mask

◆ GICDistributor_STATUSR_WROD_Pos

#define GICDistributor_STATUSR_WROD_Pos 3U

GICDistributor STATUSR: WROD Position

◆ GICDistributor_TYPER_CPUNumber

#define GICDistributor_TYPER_CPUNumber ( x ) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_CPUNumber_Pos)) & GICDistributor_TYPER_CPUNumber_Msk)

◆ GICDistributor_TYPER_CPUNumber_Msk

#define GICDistributor_TYPER_CPUNumber_Msk (0x7U << GICDistributor_TYPER_CPUNumber_Pos)

GICDistributor TYPER: CPUNumber Mask

◆ GICDistributor_TYPER_CPUNumber_Pos

#define GICDistributor_TYPER_CPUNumber_Pos 5U

GICDistributor TYPER: CPUNumber Position

◆ GICDistributor_TYPER_ITLinesNumber

#define GICDistributor_TYPER_ITLinesNumber ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_TYPER_ITLinesNumber_Pos*/)) & GICDistributor_CTLR_ITLinesNumber_Msk)

◆ GICDistributor_TYPER_ITLinesNumber_Msk

#define GICDistributor_TYPER_ITLinesNumber_Msk (0x1FU /*<< GICDistributor_TYPER_ITLinesNumber_Pos*/)

GICDistributor TYPER: ITLinesNumber Mask

◆ GICDistributor_TYPER_ITLinesNumber_Pos

#define GICDistributor_TYPER_ITLinesNumber_Pos 0U

GICDistributor TYPER: ITLinesNumber Position

◆ GICDistributor_TYPER_LSPI

#define GICDistributor_TYPER_LSPI ( x ) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_LSPI_Pos)) & GICDistributor_TYPER_LSPI_Msk)

◆ GICDistributor_TYPER_LSPI_Msk

#define GICDistributor_TYPER_LSPI_Msk (0x1FU << GICDistributor_TYPER_LSPI_Pos)

GICDistributor TYPER: LSPI Mask

◆ GICDistributor_TYPER_LSPI_Pos

#define GICDistributor_TYPER_LSPI_Pos 11U

GICDistributor TYPER: LSPI Position

◆ GICDistributor_TYPER_SecurityExtn

#define GICDistributor_TYPER_SecurityExtn ( x ) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_SecurityExtn_Pos)) & GICDistributor_TYPER_SecurityExtn_Msk)

◆ GICDistributor_TYPER_SecurityExtn_Msk

#define GICDistributor_TYPER_SecurityExtn_Msk (0x1U << GICDistributor_TYPER_SecurityExtn_Pos)

GICDistributor TYPER: SecurityExtn Mask

◆ GICDistributor_TYPER_SecurityExtn_Pos

#define GICDistributor_TYPER_SecurityExtn_Pos 10U

GICDistributor TYPER: SecurityExtn Position

◆ GICInterface_ABPR_Binary_Point

#define GICInterface_ABPR_Binary_Point ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_ABPR_Binary_Point_Pos*/)) & GICInterface_ABPR_Binary_Point_Msk)

◆ GICInterface_ABPR_Binary_Point_Msk

#define GICInterface_ABPR_Binary_Point_Msk (0x7U /*<< GICInterface_ABPR_Binary_Point_Pos*/)

PTIM ABPR: Binary_Point Mask

◆ GICInterface_ABPR_Binary_Point_Pos

#define GICInterface_ABPR_Binary_Point_Pos 0U

PTIM ABPR: Binary_Point Position

◆ GICInterface_AEOIR_INTID

#define GICInterface_AEOIR_INTID ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AEOIR_INTID_Pos*/)) & GICInterface_AEOIR_INTID_Msk)

◆ GICInterface_AEOIR_INTID_Msk

#define GICInterface_AEOIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AEOIR_INTID_Pos*/)

PTIM AEOIR: INTID Mask

◆ GICInterface_AEOIR_INTID_Pos

#define GICInterface_AEOIR_INTID_Pos 0U

PTIM AEOIR: INTID Position

◆ GICInterface_AHPPIR_INTID

#define GICInterface_AHPPIR_INTID ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AHPPIR_INTID_Pos*/)) & GICInterface_AHPPIR_INTID_Msk)

◆ GICInterface_AHPPIR_INTID_Msk

#define GICInterface_AHPPIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AHPPIR_INTID_Pos*/)

PTIM AHPPIR: INTID Mask

◆ GICInterface_AHPPIR_INTID_Pos

#define GICInterface_AHPPIR_INTID_Pos 0U

PTIM AHPPIR: INTID Position

◆ GICInterface_AIAR_INTID

#define GICInterface_AIAR_INTID ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AIAR_INTID_Pos*/)) & GICInterface_AIAR_INTID_Msk)

◆ GICInterface_AIAR_INTID_Msk

#define GICInterface_AIAR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AIAR_INTID_Pos*/)

PTIM AIAR: INTID Mask

◆ GICInterface_AIAR_INTID_Pos

#define GICInterface_AIAR_INTID_Pos 0U

PTIM AIAR: INTID Position

◆ GICInterface_BPR_Binary_Point

#define GICInterface_BPR_Binary_Point ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_BPR_Binary_Point_Pos*/)) & GICInterface_BPR_Binary_Point_Msk)

◆ GICInterface_BPR_Binary_Point_Msk

#define GICInterface_BPR_Binary_Point_Msk (0x7U /*<< GICInterface_BPR_Binary_Point_Pos*/)

PTIM BPR: Binary_Point Mask

◆ GICInterface_BPR_Binary_Point_Pos

#define GICInterface_BPR_Binary_Point_Pos 0U

PTIM BPR: Binary_Point Position

◆ GICInterface_CTLR_Enable

#define GICInterface_CTLR_Enable ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_CTLR_Enable_Pos*/)) & GICInterface_CTLR_Enable_Msk)

◆ GICInterface_CTLR_Enable_Msk

#define GICInterface_CTLR_Enable_Msk (0x1U /*<< GICInterface_CTLR_Enable_Pos*/)

PTIM CTLR: Enable Mask

◆ GICInterface_CTLR_Enable_Pos

#define GICInterface_CTLR_Enable_Pos 0U

PTIM CTLR: Enable Position

◆ GICInterface_DIR_INTID

#define GICInterface_DIR_INTID ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_DIR_INTID_Pos*/)) & GICInterface_DIR_INTID_Msk)

◆ GICInterface_DIR_INTID_Msk

#define GICInterface_DIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_DIR_INTID_Pos*/)

PTIM DIR: INTID Mask

◆ GICInterface_DIR_INTID_Pos

#define GICInterface_DIR_INTID_Pos 0U

PTIM DIR: INTID Position

◆ GICInterface_EOIR_INTID

#define GICInterface_EOIR_INTID ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_EOIR_INTID_Pos*/)) & GICInterface_EOIR_INTID_Msk)

◆ GICInterface_EOIR_INTID_Msk

#define GICInterface_EOIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_EOIR_INTID_Pos*/)

PTIM EOIR: INTID Mask

◆ GICInterface_EOIR_INTID_Pos

#define GICInterface_EOIR_INTID_Pos 0U

PTIM EOIR: INTID Position

◆ GICInterface_HPPIR_INTID

#define GICInterface_HPPIR_INTID ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_HPPIR_INTID_Pos*/)) & GICInterface_HPPIR_INTID_Msk)

◆ GICInterface_HPPIR_INTID_Msk

#define GICInterface_HPPIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_HPPIR_INTID_Pos*/)

PTIM HPPIR: INTID Mask

◆ GICInterface_HPPIR_INTID_Pos

#define GICInterface_HPPIR_INTID_Pos 0U

PTIM HPPIR: INTID Position

◆ GICInterface_IAR_INTID

#define GICInterface_IAR_INTID ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_IAR_INTID_Pos*/)) & GICInterface_IAR_INTID_Msk)

◆ GICInterface_IAR_INTID_Msk

#define GICInterface_IAR_INTID_Msk (0xFFFFFFU /*<< GICInterface_IAR_INTID_Pos*/)

PTIM IAR: INTID Mask

◆ GICInterface_IAR_INTID_Pos

#define GICInterface_IAR_INTID_Pos 0U

PTIM IAR: INTID Position

◆ GICInterface_IIDR_Arch_version

#define GICInterface_IIDR_Arch_version ( x ) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_Arch_version_Pos)) & GICInterface_IIDR_Arch_version_Msk)

◆ GICInterface_IIDR_Arch_version_Msk

#define GICInterface_IIDR_Arch_version_Msk (0xFU << GICInterface_IIDR_Arch_version_Pos)

GICInterface IIDR: Arch_version Mask

◆ GICInterface_IIDR_Arch_version_Pos

#define GICInterface_IIDR_Arch_version_Pos 16U

GICInterface IIDR: Arch_version Position

◆ GICInterface_IIDR_Implementer

#define GICInterface_IIDR_Implementer ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_IIDR_Implementer_Pos*/)) & GICInterface_IIDR_Implementer_Msk)

◆ GICInterface_IIDR_Implementer_Msk

#define GICInterface_IIDR_Implementer_Msk (0xFFFU /*<< GICInterface_IIDR_Implementer_Pos*/)

GICInterface IIDR: Implementer Mask

◆ GICInterface_IIDR_Implementer_Pos

#define GICInterface_IIDR_Implementer_Pos 0U

GICInterface IIDR: Implementer Position

◆ GICInterface_IIDR_ProductID

#define GICInterface_IIDR_ProductID ( x ) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_ProductID_Pos)) & GICInterface_IIDR_ProductID_Msk)

◆ GICInterface_IIDR_ProductID_Msk

#define GICInterface_IIDR_ProductID_Msk (0xFFFU << GICInterface_IIDR_ProductID_Pos)

GICInterface IIDR: ProductID Mask

◆ GICInterface_IIDR_ProductID_Pos

#define GICInterface_IIDR_ProductID_Pos 20U

GICInterface IIDR: ProductID Position

◆ GICInterface_IIDR_Revision

#define GICInterface_IIDR_Revision ( x ) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_Revision_Pos)) & GICInterface_IIDR_Revision_Msk)

◆ GICInterface_IIDR_Revision_Msk

#define GICInterface_IIDR_Revision_Msk (0xFU << GICInterface_IIDR_Revision_Pos)

GICInterface IIDR: Revision Mask

◆ GICInterface_IIDR_Revision_Pos

#define GICInterface_IIDR_Revision_Pos 12U

GICInterface IIDR: Revision Position

◆ GICInterface_PMR_Priority

#define GICInterface_PMR_Priority ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_PMR_Priority_Pos*/)) & GICInterface_PMR_Priority_Msk)

◆ GICInterface_PMR_Priority_Msk

#define GICInterface_PMR_Priority_Msk (0xFFU /*<< GICInterface_PMR_Priority_Pos*/)

PTIM PMR: Priority Mask

◆ GICInterface_PMR_Priority_Pos

#define GICInterface_PMR_Priority_Pos 0U

PTIM PMR: Priority Position

◆ GICInterface_RPR_INTID

#define GICInterface_RPR_INTID ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_RPR_INTID_Pos*/)) & GICInterface_RPR_INTID_Msk)

◆ GICInterface_RPR_INTID_Msk

#define GICInterface_RPR_INTID_Msk (0xFFU /*<< GICInterface_RPR_INTID_Pos*/)

PTIM RPR: INTID Mask

◆ GICInterface_RPR_INTID_Pos

#define GICInterface_RPR_INTID_Pos 0U

PTIM RPR: INTID Position

◆ GICInterface_STATUSR_ASV

#define GICInterface_STATUSR_ASV ( x ) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_ASV_Pos)) & GICInterface_STATUSR_ASV_Msk)

◆ GICInterface_STATUSR_ASV_Msk

#define GICInterface_STATUSR_ASV_Msk (0x1U << GICInterface_STATUSR_ASV_Pos)

GICInterface STATUSR: ASV Mask

◆ GICInterface_STATUSR_ASV_Pos

#define GICInterface_STATUSR_ASV_Pos 4U

GICInterface STATUSR: ASV Position

◆ GICInterface_STATUSR_RRD

#define GICInterface_STATUSR_RRD ( x ) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_STATUSR_RRD_Pos*/)) & GICInterface_STATUSR_RRD_Msk)

◆ GICInterface_STATUSR_RRD_Msk

#define GICInterface_STATUSR_RRD_Msk (0x1U /*<< GICInterface_STATUSR_RRD_Pos*/)

GICInterface STATUSR: RRD Mask

◆ GICInterface_STATUSR_RRD_Pos

#define GICInterface_STATUSR_RRD_Pos 0U

GICInterface STATUSR: RRD Position

◆ GICInterface_STATUSR_RWOD

#define GICInterface_STATUSR_RWOD ( x ) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_RWOD_Pos)) & GICInterface_STATUSR_RWOD_Msk)

◆ GICInterface_STATUSR_RWOD_Msk

#define GICInterface_STATUSR_RWOD_Msk (0x1U << GICInterface_STATUSR_RWOD_Pos)

GICInterface STATUSR: RWOD Mask

◆ GICInterface_STATUSR_RWOD_Pos

#define GICInterface_STATUSR_RWOD_Pos 2U

GICInterface STATUSR: RWOD Position

◆ GICInterface_STATUSR_WRD

#define GICInterface_STATUSR_WRD ( x ) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_WRD_Pos)) & GICInterface_STATUSR_WRD_Msk)

◆ GICInterface_STATUSR_WRD_Msk

#define GICInterface_STATUSR_WRD_Msk (0x1U << GICInterface_STATUSR_WRD_Pos)

GICInterface STATUSR: WRD Mask

◆ GICInterface_STATUSR_WRD_Pos

#define GICInterface_STATUSR_WRD_Pos 1U

GICInterface STATUSR: WRD Position

◆ GICInterface_STATUSR_WROD

#define GICInterface_STATUSR_WROD ( x ) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_WROD_Pos)) & GICInterface_STATUSR_WROD_Msk)

◆ GICInterface_STATUSR_WROD_Msk

#define GICInterface_STATUSR_WROD_Msk (0x1U << GICInterface_STATUSR_WROD_Pos)

GICInterface STATUSR: WROD Mask

◆ GICInterface_STATUSR_WROD_Pos

#define GICInterface_STATUSR_WROD_Pos 3U

GICInterface STATUSR: WROD Position

◆ OFFSET_1M

#define OFFSET_1M (0x00100000)

◆ OFFSET_4K

#define OFFSET_4K (0x00001000)

◆ OFFSET_64K

#define OFFSET_64K (0x00010000)

◆ PAGE_4K_B_SHIFT

#define PAGE_4K_B_SHIFT (2)

◆ PAGE_4K_C_SHIFT

#define PAGE_4K_C_SHIFT (3)

◆ PAGE_4K_TEX0_SHIFT

#define PAGE_4K_TEX0_SHIFT (6)

◆ PAGE_4K_TEX1_SHIFT

#define PAGE_4K_TEX1_SHIFT (7)

◆ PAGE_4K_TEX2_SHIFT

#define PAGE_4K_TEX2_SHIFT (8)

◆ PAGE_4K_TEXCB_MASK

#define PAGE_4K_TEXCB_MASK (0xFFFFFE33)

◆ PAGE_64K_B_SHIFT

#define PAGE_64K_B_SHIFT (2)

◆ PAGE_64K_C_SHIFT

#define PAGE_64K_C_SHIFT (3)

◆ PAGE_64K_TEX0_SHIFT

#define PAGE_64K_TEX0_SHIFT (12)

◆ PAGE_64K_TEX1_SHIFT

#define PAGE_64K_TEX1_SHIFT (13)

◆ PAGE_64K_TEX2_SHIFT

#define PAGE_64K_TEX2_SHIFT (14)

◆ PAGE_64K_TEXCB_MASK

#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)

◆ PAGE_AP2_SHIFT

#define PAGE_AP2_SHIFT (9)

◆ PAGE_AP_MASK

#define PAGE_AP_MASK (0xFFFFFDCF)

◆ PAGE_AP_SHIFT

#define PAGE_AP_SHIFT (4)

◆ PAGE_B_SHIFT

#define PAGE_B_SHIFT (2)

◆ PAGE_C_SHIFT

#define PAGE_C_SHIFT (3)

◆ PAGE_DOMAIN_MASK

#define PAGE_DOMAIN_MASK (0xFFFFFE1F)

◆ PAGE_DOMAIN_SHIFT

#define PAGE_DOMAIN_SHIFT (5)

◆ PAGE_L1_DESCRIPTOR

#define PAGE_L1_DESCRIPTOR (0x1)

◆ PAGE_L1_MASK

#define PAGE_L1_MASK (0xFFFFFFFC)

◆ PAGE_L2_4K_DESC

#define PAGE_L2_4K_DESC (0x2)

◆ PAGE_L2_4K_MASK

#define PAGE_L2_4K_MASK (0xFFFFFFFD)

◆ PAGE_L2_64K_DESC

#define PAGE_L2_64K_DESC (0x1)

◆ PAGE_L2_64K_MASK

#define PAGE_L2_64K_MASK (0xFFFFFFFC)

◆ PAGE_NG_MASK

#define PAGE_NG_MASK (0xFFFFF7FF)

◆ PAGE_NG_SHIFT

#define PAGE_NG_SHIFT (11)

◆ PAGE_NS_MASK

#define PAGE_NS_MASK (0xFFFFFFF7)

◆ PAGE_NS_SHIFT

#define PAGE_NS_SHIFT (3)

◆ PAGE_P_MASK

#define PAGE_P_MASK (0xFFFFFDFF)

◆ PAGE_P_SHIFT

#define PAGE_P_SHIFT (9)

◆ PAGE_S_MASK

#define PAGE_S_MASK (0xFFFFFBFF)

◆ PAGE_S_SHIFT

#define PAGE_S_SHIFT (10)

◆ PAGE_TEX_SHIFT

#define PAGE_TEX_SHIFT (12)

◆ PAGE_TEXCB_MASK

#define PAGE_TEXCB_MASK (0xFFFF8FF3)

◆ PAGE_XN_4K_MASK

#define PAGE_XN_4K_MASK (0xFFFFFFFE)

◆ PAGE_XN_4K_SHIFT

#define PAGE_XN_4K_SHIFT (0)

◆ PAGE_XN_64K_MASK

#define PAGE_XN_64K_MASK (0xFFFF7FFF)

◆ PAGE_XN_64K_SHIFT

#define PAGE_XN_64K_SHIFT (15)

◆ PTIM_CONTROL_AutoReload

#define PTIM_CONTROL_AutoReload ( x ) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_AutoReload_Pos)) & PTIM_CONTROL_AutoReload_Msk)

◆ PTIM_CONTROL_AutoReload_Msk

#define PTIM_CONTROL_AutoReload_Msk (0x1U << PTIM_CONTROL_AutoReload_Pos)

PTIM CONTROL: Auto Reload Mask

◆ PTIM_CONTROL_AutoReload_Pos

#define PTIM_CONTROL_AutoReload_Pos 1U

PTIM CONTROL: Auto Reload Position

◆ PTIM_CONTROL_Enable

#define PTIM_CONTROL_Enable ( x ) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_CONTROL_Enable_Pos*/)) & PTIM_CONTROL_Enable_Msk)

◆ PTIM_CONTROL_Enable_Msk

#define PTIM_CONTROL_Enable_Msk (0x1U /*<< PTIM_CONTROL_Enable_Pos*/)

PTIM CONTROL: Enable Mask

◆ PTIM_CONTROL_Enable_Pos

#define PTIM_CONTROL_Enable_Pos 0U

PTIM CONTROL: Enable Position

◆ PTIM_CONTROL_IRQenable

#define PTIM_CONTROL_IRQenable ( x ) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_IRQenable_Pos)) & PTIM_CONTROL_IRQenable_Msk)

◆ PTIM_CONTROL_IRQenable_Msk

#define PTIM_CONTROL_IRQenable_Msk (0x1U << PTIM_CONTROL_IRQenable_Pos)

PTIM CONTROL: IRQ Enabel Mask

◆ PTIM_CONTROL_IRQenable_Pos

#define PTIM_CONTROL_IRQenable_Pos 2U

PTIM CONTROL: IRQ Enabel Position

◆ PTIM_CONTROL_Prescaler

#define PTIM_CONTROL_Prescaler ( x ) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_Prescaler_Pos)) & PTIM_CONTROL_Prescaler_Msk)

◆ PTIM_CONTROL_Prescaler_Msk

#define PTIM_CONTROL_Prescaler_Msk (0xFFU << PTIM_CONTROL_Prescaler_Pos)

PTIM CONTROL: Prescaler Mask

◆ PTIM_CONTROL_Prescaler_Pos

#define PTIM_CONTROL_Prescaler_Pos 8U

PTIM CONTROL: Prescaler Position

◆ PTIM_WCONTROL_AutoReload

#define PTIM_WCONTROL_AutoReload ( x ) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_AutoReload_Pos)) & PTIM_WCONTROL_AutoReload_Msk)

◆ PTIM_WCONTROL_AutoReload_Msk

#define PTIM_WCONTROL_AutoReload_Msk (0x1U << PTIM_WCONTROL_AutoReload_Pos)

PTIM WCONTROL: Auto Reload Mask

◆ PTIM_WCONTROL_AutoReload_Pos

#define PTIM_WCONTROL_AutoReload_Pos 1U

PTIM WCONTROL: Auto Reload Position

◆ PTIM_WCONTROL_Enable

#define PTIM_WCONTROL_Enable ( x ) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WCONTROL_Enable_Pos*/)) & PTIM_WCONTROL_Enable_Msk)

◆ PTIM_WCONTROL_Enable_Msk

#define PTIM_WCONTROL_Enable_Msk (0x1U /*<< PTIM_WCONTROL_Enable_Pos*/)

PTIM WCONTROL: Enable Mask

◆ PTIM_WCONTROL_Enable_Pos

#define PTIM_WCONTROL_Enable_Pos 0U

PTIM WCONTROL: Enable Position

◆ PTIM_WCONTROL_IRQenable

#define PTIM_WCONTROL_IRQenable ( x ) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_IRQenable_Pos)) & PTIM_WCONTROL_IRQenable_Msk)

◆ PTIM_WCONTROL_IRQenable_Msk

#define PTIM_WCONTROL_IRQenable_Msk (0x1U << PTIM_WCONTROL_IRQenable_Pos)

PTIM WCONTROL: IRQ Enable Mask

◆ PTIM_WCONTROL_IRQenable_Pos

#define PTIM_WCONTROL_IRQenable_Pos 2U

PTIM WCONTROL: IRQ Enable Position

◆ PTIM_WCONTROL_Mode

#define PTIM_WCONTROL_Mode ( x ) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_Mode_Pos)) & PTIM_WCONTROL_Mode_Msk)

◆ PTIM_WCONTROL_Mode_Msk

#define PTIM_WCONTROL_Mode_Msk (0x1U << PTIM_WCONTROL_Mode_Pos)

PTIM WCONTROL: Watchdog Mode Mask

◆ PTIM_WCONTROL_Mode_Pos

#define PTIM_WCONTROL_Mode_Pos 3U

PTIM WCONTROL: Watchdog Mode Position

◆ PTIM_WCONTROL_Presacler

#define PTIM_WCONTROL_Presacler ( x ) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_Presacler_Pos)) & PTIM_WCONTROL_Presacler_Msk)

◆ PTIM_WCONTROL_Presacler_Msk

#define PTIM_WCONTROL_Presacler_Msk (0xFFU << PTIM_WCONTROL_Presacler_Pos)

PTIM WCONTROL: Prescaler Mask

◆ PTIM_WCONTROL_Presacler_Pos

#define PTIM_WCONTROL_Presacler_Pos 8U

PTIM WCONTROL: Prescaler Position

◆ PTIM_WISR_EventFlag

#define PTIM_WISR_EventFlag ( x ) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WISR_EventFlag_Pos*/)) & PTIM_WISR_EventFlag_Msk)

◆ PTIM_WISR_EventFlag_Msk

#define PTIM_WISR_EventFlag_Msk (0x1U /*<< PTIM_WISR_EventFlag_Pos*/)

PTIM WISR: Event Flag Mask

◆ PTIM_WISR_EventFlag_Pos

#define PTIM_WISR_EventFlag_Pos 0U

PTIM WISR: Event Flag Position

◆ PTIM_WRESET_ResetFlag

#define PTIM_WRESET_ResetFlag ( x ) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WRESET_ResetFlag_Pos*/)) & PTIM_WRESET_ResetFlag_Msk)

◆ PTIM_WRESET_ResetFlag_Msk

#define PTIM_WRESET_ResetFlag_Msk (0x1U /*<< PTIM_WRESET_ResetFlag_Pos*/)

PTIM WRESET: Reset Flag Mask

◆ PTIM_WRESET_ResetFlag_Pos

#define PTIM_WRESET_ResetFlag_Pos 0U

PTIM WRESET: Reset Flag Position

◆ RESERVED

#define RESERVED	(	N,
		T
	)	T RESERVED##N;

◆ SECTION_AP2_SHIFT

#define SECTION_AP2_SHIFT (15)

◆ SECTION_AP_MASK

#define SECTION_AP_MASK (0xFFFF73FF)

◆ SECTION_AP_SHIFT

#define SECTION_AP_SHIFT (10)

◆ SECTION_DOMAIN_MASK

#define SECTION_DOMAIN_MASK (0xFFFFFE1F)

◆ SECTION_DOMAIN_SHIFT

#define SECTION_DOMAIN_SHIFT (5)

◆ SECTION_MASK

#define SECTION_MASK (0xFFFFFFFC)

◆ SECTION_NG_MASK

#define SECTION_NG_MASK (0xFFFDFFFF)

◆ SECTION_NG_SHIFT

#define SECTION_NG_SHIFT (17)

◆ section_normal_nc

#define section_normal_nc	(	descriptor_l1,
		region
	)

◆ SECTION_NS_MASK

#define SECTION_NS_MASK (0xFFF7FFFF)

◆ SECTION_NS_SHIFT

#define SECTION_NS_SHIFT (19)

◆ SECTION_P_MASK

#define SECTION_P_MASK (0xFFFFFDFF)

◆ SECTION_P_SHIFT

#define SECTION_P_SHIFT (9)

◆ SECTION_S_MASK

#define SECTION_S_MASK (0xFFFEFFFF)

◆ SECTION_S_SHIFT

#define SECTION_S_SHIFT (16)

◆ SECTION_TEX0_SHIFT

#define SECTION_TEX0_SHIFT (12)

◆ SECTION_TEX1_SHIFT

#define SECTION_TEX1_SHIFT (13)

◆ SECTION_TEX2_SHIFT

#define SECTION_TEX2_SHIFT (14)

◆ SECTION_TEXCB_MASK

#define SECTION_TEXCB_MASK (0xFFFF8FF3)

◆ SECTION_XN_MASK

#define SECTION_XN_MASK (0xFFFFFFEF)

◆ SECTION_XN_SHIFT

#define SECTION_XN_SHIFT (4)

Function Documentation

◆ __L1C_MaintainDCacheSetWay()

__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay	(	uint32_t	level,
		uint32_t	maint
	)

Apply cache maintenance to given cache level.

Parameters

[in]	level	cache level to be maintained
[in]	maint	0 - invalidate, 1 - clean, otherwise - invalidate and clean

◆ __log2_up()

__STATIC_FORCEINLINE uint8_t __log2_up ( uint32_t n )

Calculate log2 rounded up.

log(0) => 0
log(1) => 0
log(2) => 1
log(3) => 2
log(4) => 2
log(5) => 3 : :
log(16) => 4
log(32) => 5 : :
Parameters

[in] n input value parameter

Returns
log2(n)

◆ GIC_GetConfiguration()

__STATIC_INLINE uint32_t GIC_GetConfiguration ( IRQn_Type IRQn )

Get the interrupt configuration from the GIC's ICFGR register.

Parameters

[in] IRQn Interrupt to acquire the configuration for.

Returns: Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) Bit 1: 0 - level sensitive, 1 - edge triggered

◆ GIC_GetEnableIRQ()

__STATIC_INLINE uint32_t GIC_GetEnableIRQ ( IRQn_Type IRQn )

Get interrupt enable status using GIC's ISENABLER register.

Parameters

[in] IRQn The interrupt to be queried.

Returns: 0 - interrupt is not enabled, 1 - interrupt is enabled.

◆ GIC_GetGroup()

__STATIC_INLINE uint32_t GIC_GetGroup ( IRQn_Type IRQn )

Get the interrupt group from the GIC's IGROUPR register.

Parameters

[in] IRQn The interrupt to be queried.

Returns: 0 - Group 0, 1 - Group 1

◆ GIC_GetPendingIRQ()

__STATIC_INLINE uint32_t GIC_GetPendingIRQ ( IRQn_Type IRQn )

Get interrupt pending status from GIC's ISPENDR register.

Parameters

[in] IRQn The interrupt to be queried.

Returns: 0 - interrupt is not pending, 1 - interrupt is pendig.

◆ GIC_SetConfiguration()

__STATIC_INLINE void GIC_SetConfiguration	(	IRQn_Type	IRQn,
		uint32_t	int_config
	)

Sets the interrupt configuration using GIC's ICFGR register.

Parameters

[in]	IRQn	The interrupt to be configured.
[in]	int_config	Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) Bit 1: 0 - level sensitive, 1 - edge triggered

◆ GIC_SetGroup()

__STATIC_INLINE void GIC_SetGroup	(	IRQn_Type	IRQn,
		uint32_t	group
	)

Set the interrupt group from the GIC's IGROUPR register.

Parameters

[in]	IRQn	The interrupt to be queried.
[in]	group	Interrupt group number: 0 - Group 0, 1 - Group 1

◆ L1C_InvalidateICacheMVA()

__STATIC_FORCEINLINE void L1C_InvalidateICacheMVA ( void * va )

Clean instruction cache line by address.

Parameters

[in] va Pointer to instructions to clear the cache for.

◆ PTIM_GetEventFlag()

__STATIC_INLINE uint32_t PTIM_GetEventFlag ( void )

ref Timer_Type::CONTROL Get the event flag in timers ISR register.

Returns: 0 - flag is not set, 1- flag is set

◆ PTIM_SetCurrentValue()

__STATIC_INLINE void PTIM_SetCurrentValue ( uint32_t value )

Set current counter value from its COUNTER register.

◆ VL1_GetControl()

__STATIC_INLINE uint32_t VL1_GetControl ( void )

Get the virtual timer control value.

Returns: Virtual timer control value.

◆ VL1_GetCurrentCountValue()

__STATIC_INLINE uint64_t VL1_GetCurrentCountValue ( void )

Get the current virtual count value.

Returns: Current virtual count value.

◆ VL1_GetCurrentTimerValue()

__STATIC_INLINE uint32_t VL1_GetCurrentTimerValue ( void )

Get the current virtual timer value.

Returns: Current virtual timer value.

◆ VL1_GetTimerCompareValue()

__STATIC_INLINE uint64_t VL1_GetTimerCompareValue ( void )

Get the virtual timer compare value.

Returns: Virtual timer compare value.

◆ VL1_SetControl()

__STATIC_INLINE void VL1_SetControl ( uint32_t value )

Configure the virtual timer by setting the control value.

Parameters

[in] value New virtual timer control value.

◆ VL1_SetCurrentTimerValue()

__STATIC_INLINE void VL1_SetCurrentTimerValue ( uint32_t value )

Virtual Timer Control register.

Sets the reset value of the virtual timer.

Parameters

[in] value The value the virtual timer is loaded with.

◆ VL1_SetTimerCompareValue()

__STATIC_INLINE void VL1_SetTimerCompareValue ( uint64_t value )

Set the virtual timer compare value.

Parameters

[in] value New virtual timer compare value.

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

◆ __CORE_CA_H_DEPENDANT

◆ __FPU_PRESENT

◆ __FPU_USED

◆ __GIC_PRESENT

◆ __I

◆ __IM

◆ __IO

◆ __IOM

◆ __O

◆ __OM

◆ __TIM_PRESENT

◆ _FLD2VAL

◆ _VAL2FLD

◆ DESCRIPTOR_FAULT

◆ GIC_GetSecurity

◆ GIC_SetSecurity

◆ GICDistributor_CLRSPI_NSR_INTID

◆ GICDistributor_CLRSPI_NSR_INTID_Msk

◆ GICDistributor_CLRSPI_NSR_INTID_Pos

◆ GICDistributor_CLRSPI_SR_INTID

◆ GICDistributor_CLRSPI_SR_INTID_Msk

◆ GICDistributor_CLRSPI_SR_INTID_Pos

◆ GICDistributor_CTLR_ARE

◆ GICDistributor_CTLR_ARE_Msk

◆ GICDistributor_CTLR_ARE_Pos

◆ GICDistributor_CTLR_DC

◆ GICDistributor_CTLR_DC_Msk

◆ GICDistributor_CTLR_DC_Pos

◆ GICDistributor_CTLR_EINWF

◆ GICDistributor_CTLR_EINWF_Msk

◆ GICDistributor_CTLR_EINWF_Pos

◆ GICDistributor_CTLR_EnableGrp0

◆ GICDistributor_CTLR_EnableGrp0_Msk

◆ GICDistributor_CTLR_EnableGrp0_Pos

◆ GICDistributor_CTLR_EnableGrp1

◆ GICDistributor_CTLR_EnableGrp1_Msk

◆ GICDistributor_CTLR_EnableGrp1_Pos

◆ GICDistributor_CTLR_RWP

◆ GICDistributor_CTLR_RWP_Msk

◆ GICDistributor_CTLR_RWP_Pos

◆ GICDistributor_IIDR_Implementer

◆ GICDistributor_IIDR_Implementer_Msk

◆ GICDistributor_IIDR_Implementer_Pos

◆ GICDistributor_IIDR_ProductID

◆ GICDistributor_IIDR_ProductID_Msk

◆ GICDistributor_IIDR_ProductID_Pos

◆ GICDistributor_IIDR_Revision

◆ GICDistributor_IIDR_Revision_Msk

◆ GICDistributor_IIDR_Revision_Pos

◆ GICDistributor_IIDR_Variant

◆ GICDistributor_IIDR_Variant_Msk

◆ GICDistributor_IIDR_Variant_Pos

◆ GICDistributor_IROUTER_Aff0

◆ GICDistributor_IROUTER_Aff0_Msk

◆ GICDistributor_IROUTER_Aff0_Pos

◆ GICDistributor_IROUTER_Aff1

◆ GICDistributor_IROUTER_Aff1_Msk

◆ GICDistributor_IROUTER_Aff1_Pos

◆ GICDistributor_IROUTER_Aff2

◆ GICDistributor_IROUTER_Aff2_Msk

◆ GICDistributor_IROUTER_Aff2_Pos

◆ GICDistributor_IROUTER_Aff3

◆ GICDistributor_IROUTER_Aff3_Msk

◆ GICDistributor_IROUTER_Aff3_Pos

◆ GICDistributor_IROUTER_IRM

◆ GICDistributor_IROUTER_IRM_Msk

◆ GICDistributor_IROUTER_IRM_Pos

◆ GICDistributor_ITARGETSR_CPU0

◆ GICDistributor_ITARGETSR_CPU0_Msk

◆ GICDistributor_ITARGETSR_CPU0_Pos

◆ GICDistributor_ITARGETSR_CPU1

◆ GICDistributor_ITARGETSR_CPU1_Msk

◆ GICDistributor_ITARGETSR_CPU1_Pos

◆ GICDistributor_ITARGETSR_CPU2

◆ GICDistributor_ITARGETSR_CPU2_Msk