CMSIS-Core (Cortex-A)  
CMSIS-Core support for Cortex-A processor-based devices
 
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Generic Interrupt Controller Functions

The Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC). More...

Data Structures

struct  GICInterface_Type
 Structure type to access the Generic Interrupt Controller Interface (GICC) More...
 
struct  GICDistributor_Type
 Structure type to access the Generic Interrupt Controller Distributor (GICD) More...
 

Macros

#define GICDistributor   ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE )
 GIC Distributor register set access pointer.
 
#define GICInterface   ((GICInterface_Type *) GIC_INTERFACE_BASE )
 GIC Interface register set access pointer.
 

Functions

__STATIC_INLINE void GIC_EnableDistributor (void)
 Enable the interrupt distributor using the GIC's CTLR register.
 
__STATIC_INLINE void GIC_DisableDistributor (void)
 Disable the interrupt distributor using the GIC's CTLR register.
 
__STATIC_INLINE uint32_t GIC_DistributorInfo (void)
 Read the GIC's TYPER register.
 
__STATIC_INLINE uint32_t GIC_DistributorImplementer (void)
 Reads the GIC's IIDR register.
 
__STATIC_INLINE void GIC_SetTarget (IRQn_Type IRQn, uint32_t cpu_target)
 Sets the GIC's ITARGETSR register for the given interrupt.
 
__STATIC_INLINE uint32_t GIC_GetTarget (IRQn_Type IRQn)
 Read the GIC's ITARGETSR register.
 
__STATIC_INLINE void GIC_EnableInterface (void)
 Enable the CPU's interrupt interface.
 
__STATIC_INLINE void GIC_DisableInterface (void)
 Disable the CPU's interrupt interface.
 
__STATIC_INLINE IRQn_Type GIC_AcknowledgePending (void)
 Read the CPU's IAR register.
 
__STATIC_INLINE void GIC_EndInterrupt (IRQn_Type IRQn)
 Writes the given interrupt number to the CPU's EOIR register.
 
__STATIC_INLINE void GIC_EnableIRQ (IRQn_Type IRQn)
 Enables the given interrupt using GIC's ISENABLER register.
 
__STATIC_INLINE void GIC_DisableIRQ (IRQn_Type IRQn)
 Disables the given interrupt using GIC's ICENABLER register.
 
__STATIC_INLINE void GIC_SetPendingIRQ (IRQn_Type IRQn)
 Sets the given interrupt as pending using GIC's ISPENDR register.
 
__STATIC_INLINE void GIC_ClearPendingIRQ (IRQn_Type IRQn)
 Clears the given interrupt from being pending using GIC's ICPENDR register.
 
__STATIC_INLINE void GIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
 Set the priority for the given interrupt in the GIC's IPRIORITYR register.
 
__STATIC_INLINE uint32_t GIC_GetPriority (IRQn_Type IRQn)
 Read the current interrupt priority from GIC's IPRIORITYR register.
 
__STATIC_INLINE void GIC_SetInterfacePriorityMask (uint32_t priority)
 Set the interrupt priority mask using CPU's PMR register.
 
__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask (void)
 Read the current interrupt priority mask from CPU's PMR register.
 
__STATIC_INLINE void GIC_SetBinaryPoint (uint32_t binary_point)
 Configures the group priority and subpriority split point using CPU's BPR register.
 
__STATIC_INLINE uint32_t GIC_GetBinaryPoint (void)
 Read the current group priority and subpriority split point from CPU's BPR register.
 
__STATIC_INLINE uint32_t GIC_GetIRQStatus (IRQn_Type IRQn)
 Get the status for a given interrupt.
 
__STATIC_INLINE void GIC_SendSGI (IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
 Generate a software interrupt using GIC's SGIR register.
 
__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ (void)
 Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.
 
__STATIC_INLINE uint32_t GIC_GetInterfaceId (void)
 Provides information about the implementer and revision of the CPU interface.
 
__STATIC_INLINE void GIC_DistInit (void)
 Initialize the interrupt distributor.
 
__STATIC_INLINE void GIC_CPUInterfaceInit (void)
 Initialize the CPU's interrupt interface.
 
__STATIC_INLINE void GIC_Enable (void)
 Initialize and enable the GIC.
 

Description

The Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC).

Reference: Generic Interrupt Controller Architecture Specificaton.

The following table shows the register naming of CMSIS in correlation with various technical reference manuals.

CMSIS Register Name Cortex-A5 TRM Cortex-A7 TRM Cortex-A9 TRM
GIC Distributor
GICDistributor->CTLR ICDDCR GICD_CTLR ICDDCR
GICDistributor->TYPER ICDICTR GICD_TYPER ICDICTR
GICDistributor->IIDR ICDIIDR GICD_IIDR ICDIIDR
GICDistributor->STATUSR
GICDistributor->SETSPI_NSR
GICDistributor->CLRSPI_NSR
GICDistributor->IGROUPR[] ICDISR GICD_IGROUPRn ICDISRn
GICDistributor->ISENABLER[] ICDISER GICD_ISENABLERn ICDISERn
GICDistributor->ICENABLER[] ICDICER GICD_ICENABLERn ICDICERn
GICDistributor->ISPENDR[] ICDISPR GICD_ISPENDRn ICDISPRn
GICDistributor->ICPENDR[] ICDICPR GICD_ICPENDRn ICDICPRn
GICDistributor->ISACTIVER[] ICDABR GICD_ISACTIVERn ICDABRn
GICDistributor->ICACTIVER[] GICD_ICACTIVERn
GICDistributor->IPRIORITYR[] ICDIPR GICD_IPRIORITYRn ICDIPRn
GICDistributor->ITARGETSR[] ICDIPTR GICD_ITARGETSRn ICDIPTRn
GICDistributor->ICFGR[] ICDICFR GICD_ICFGRn ICDICFRn
GICDistributor->IGRPMODR[0] ICDPPIS GICD_PPISR ppi_status
GICDistributor->IGRPMODR[31:1] ICDSPIS GICD_SPISRn spi_status
GICDistributor->NSACR[]
GICDistributor->SGIR ICDSGIR GICD_SGIR ICDSGIR
GICDistributor->CPENDSGIR[] GICD_CPENDSGIRn
GICDistributor->SPENDSGIR[] GICD_SPENDSGIRn
GICDistributor->IROUTER[]
GIC Interface
GICInterface->CTLR ICPICR GICC_CTLR ICCICR
GICInterface->PMR ICCIPMR GICC_PMRn ICCPMR
GICInterface->BPR ICCBPR GICC_BPR ICCBPR
GICInterface->IAR ICCIAR GICC_IAR ICCIAR
GICInterface->EOIR ICCEOIR GICC_EOIR ICCEOIR
GICInterface->RPR ICCRPR GICC_RPR ICCRPR
GICInterface->HPPIR ICCHPIR GICC_HPPIR ICCHPIR
GICInterface->ABPR ICCABPR GICC_ABPR ICCABPR
GICInterface->AIAR GICC_AIAR
GICInterface->AEOIR GICC_AEOIR
GICInterface->AHPPIR GICC_AHPPIR
GICInterface->STATUSR
GICInterface->APR[] GICC_APR0
GICInterface->NSAPR[] GICC_NSAPR0
GICInterface->IIDR ICCIIDR GICC_IIDR ICCIDR
GICInterface->DIR GICC_DIR

Macro Definition Documentation

◆ GICDistributor

#define GICDistributor   ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE )

GIC Distributor register set access pointer.

Use GICDistributor to access the GIC Distributor registers.

Example:

GICDistributor->CTRL |= 1; // Enable group 0 interrupts
#define GICDistributor
GIC Distributor register set access pointer.

◆ GICInterface

#define GICInterface   ((GICInterface_Type *) GIC_INTERFACE_BASE )

GIC Interface register set access pointer.

Use GICInterface to access the GIC Interface registers.

Example:

GICInterface->CTLR |= 1; // Enable interrupt signaling
#define GICInterface
GIC Interface register set access pointer.

Function Documentation

◆ GIC_AcknowledgePending()

__STATIC_INLINE IRQn_Type GIC_AcknowledgePending ( void  )

Read the CPU's IAR register.

Returns
GICInterface_Type::IAR

Provides the interrupt number of the highest priority interrupt pending. A read of this register acts as an acknowledge for the interrupt.

The read returns a spurious interrupt number of 1023 if any of the following apply:

  • Forwarding of interrupts by the Distributor to the CPU interface is disabled.
  • Signaling of interrupts by the CPU interface to the connected PE is disabled.
  • There are no pending interrupts on the CPU interface with sufficient priority for the interface to signal it to the PE.
See also
GIC_EndInterrupt

◆ GIC_ClearPendingIRQ()

__STATIC_INLINE void GIC_ClearPendingIRQ ( IRQn_Type  IRQn)

Clears the given interrupt from being pending using GIC's ICPENDR register.

Parameters
[in]IRQnThe interrupt to be enabled.

Removes the pending state from the corresponding interrupt.

◆ GIC_CPUInterfaceInit()

__STATIC_INLINE void GIC_CPUInterfaceInit ( void  )

Initialize the CPU's interrupt interface.

All software generated (SGIs) and private peripheral interrupts (PPIs) are initialized to be

  • disabled
  • level-sensitive, 1-N model
  • priority 0x7F and the interrupt interface is enabled.

The binary point is set to zero.

The interrupt priority mask is set to 0xFF.

See also
GIC_DisableIRQ
GIC_SetLevelModel
GIC_SetPriority
GIC_EnableInterface
GIC_SetBinaryPoint
GIC_SetInterfacePriorityMask

◆ GIC_DisableDistributor()

__STATIC_INLINE void GIC_DisableDistributor ( void  )

Disable the interrupt distributor using the GIC's CTLR register.

Globally disable the forwarding of interrupts to the CPU interfaces.

See also
GIC_EnableDistributor

◆ GIC_DisableInterface()

__STATIC_INLINE void GIC_DisableInterface ( void  )

Disable the CPU's interrupt interface.

Resets the Enable bit in the local CPUs CTLR register. Only the CPU executing the call is affected.

◆ GIC_DisableIRQ()

__STATIC_INLINE void GIC_DisableIRQ ( IRQn_Type  IRQn)

Disables the given interrupt using GIC's ICENABLER register.

Parameters
[in]IRQnThe interrupt to be disabled.

Disables forwarding of the corresponding interrupt to the CPU interfaces.

◆ GIC_DistInit()

__STATIC_INLINE void GIC_DistInit ( void  )

Initialize the interrupt distributor.

All shared peripheral interrupts (SPIs) are initialized to be

  • disabled
  • level-sensitive, 1-N model
  • priority 0x7F
  • targeting CPU0 and the distributor is enabled.
See also
GIC_DisableIRQ
GIC_SetLevelModel
GIC_SetPriority
GIC_SetTarget
GIC_EnableDistributor

◆ GIC_DistributorImplementer()

__STATIC_INLINE uint32_t GIC_DistributorImplementer ( void  )

Reads the GIC's IIDR register.

Returns
GICDistributor_Type::IIDR

Provides information about the implementer and revision of the Distributor.

◆ GIC_DistributorInfo()

__STATIC_INLINE uint32_t GIC_DistributorInfo ( void  )

Read the GIC's TYPER register.

Returns
GICDistributor_Type::TYPER

Provides information about the configuration of the GIC. It indicates:

  • whether the GIC implements the Security Extensions
  • the maximum number of interrupt IDs that the GIC supports
  • the number of CPU interfaces implemented
  • if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).

◆ GIC_Enable()

__STATIC_INLINE void GIC_Enable ( void  )

Initialize and enable the GIC.

Initializes the distributor and the cpu interface.

See also
GIC_DistInit GIC_CPUInterfaceInit

◆ GIC_EnableDistributor()

__STATIC_INLINE void GIC_EnableDistributor ( void  )

Enable the interrupt distributor using the GIC's CTLR register.

Globally enable the forwarding of interrupts to the CPU interfaces.

◆ GIC_EnableInterface()

__STATIC_INLINE void GIC_EnableInterface ( void  )

Enable the CPU's interrupt interface.

Sets the Enable bit in the local CPUs CTLR register. Only the CPU executing the call is affected.

◆ GIC_EnableIRQ()

__STATIC_INLINE void GIC_EnableIRQ ( IRQn_Type  IRQn)

Enables the given interrupt using GIC's ISENABLER register.

Parameters
[in]IRQnThe interrupt to be enabled.

Enables forwarding of the corresponding interrupt to the CPU interfaces.

◆ GIC_EndInterrupt()

__STATIC_INLINE void GIC_EndInterrupt ( IRQn_Type  IRQn)

Writes the given interrupt number to the CPU's EOIR register.

Parameters
[in]IRQnThe interrupt to be signaled as finished.

A write to this register performs priority drop for the specified interrupt.

For nested interrupts, the order of calls to this function must be the reverse of the order of interrupt acknowledgement, i.e. calls to GIC_AcknowledgePending. Behavior is UNPREDICTABLE if:

  • This ordering constraint is not maintained.
  • The given interrupt number does not match an active interrupt, or the ID of a spurious interrupt.
  • The given interrupt number does not match the last valid interrupt value returned by GIC_AcknowledgePending.

◆ GIC_GetBinaryPoint()

__STATIC_INLINE uint32_t GIC_GetBinaryPoint ( void  )

Read the current group priority and subpriority split point from CPU's BPR register.

Returns
GICInterface_Type::BPR
See also
GIC_SetBinaryPoint

◆ GIC_GetHighPendingIRQ()

__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ ( void  )

Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.

Returns
GICInterface_Type::HPPIR

◆ GIC_GetInterfaceId()

__STATIC_INLINE uint32_t GIC_GetInterfaceId ( void  )

Provides information about the implementer and revision of the CPU interface.

Returns
GICInterface_Type::IIDR

◆ GIC_GetInterfacePriorityMask()

__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask ( void  )

Read the current interrupt priority mask from CPU's PMR register.

Returns
GICInterface_Type::PMR
See also
GIC_SetInterfacePriorityMask

◆ GIC_GetIRQStatus()

__STATIC_INLINE uint32_t GIC_GetIRQStatus ( IRQn_Type  IRQn)

Get the status for a given interrupt.

Parameters
[in]IRQnThe interrupt to get status for.
Returns
0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active

The return value is a combination of GIC's ISACTIVER and ISPENDR registers.

Bit 0 denotes interrupts pending bit (interrupt should be handled) and bit 1 denotes interrupts active bit (interrupt is currently handled).

◆ GIC_GetPriority()

__STATIC_INLINE uint32_t GIC_GetPriority ( IRQn_Type  IRQn)

Read the current interrupt priority from GIC's IPRIORITYR register.

Parameters
[in]IRQnThe interrupt to be queried.

Can be used to retrieve the actual priority depending on the GIC implementation.

See also
GIC_SetPriority

◆ GIC_GetTarget()

__STATIC_INLINE uint32_t GIC_GetTarget ( IRQn_Type  IRQn)

Read the GIC's ITARGETSR register.

Parameters
[in]IRQnInterrupt to acquire the configuration for.
Returns
GICDistributor_Type::ITARGETSR

Read the current interrupt to CPU assignment for the given interrupt.

See also
GIC_SetTarget

◆ GIC_SendSGI()

__STATIC_INLINE void GIC_SendSGI ( IRQn_Type  IRQn,
uint32_t  target_list,
uint32_t  filter_list 
)

Generate a software interrupt using GIC's SGIR register.

Parameters
[in]IRQnSoftware interrupt to be generated.
[in]target_listList of CPUs the software interrupt should be forwarded to.
[in]filter_listFilter to be applied to determine interrupt receivers.

◆ GIC_SetBinaryPoint()

__STATIC_INLINE void GIC_SetBinaryPoint ( uint32_t  binary_point)

Configures the group priority and subpriority split point using CPU's BPR register.

Parameters
[in]binary_pointAmount of bits used as subpriority.

The binary point defines the amount of priority bits used as a group priority and subpriorities.

Interrupts sharing the same group priority do not preempt each other. But interrupts having a higher group priority (lower value) preempt interrups with a lower group priority.

The subpriority defines the execution sequence of interrupts with the same group priority if multiple are pending at time.

◆ GIC_SetInterfacePriorityMask()

__STATIC_INLINE void GIC_SetInterfacePriorityMask ( uint32_t  priority)

Set the interrupt priority mask using CPU's PMR register.

Parameters
[in]priorityPriority mask to be set.

Only interrupts with a higher priority (lower values) than the value provided are signaled.

◆ GIC_SetPendingIRQ()

__STATIC_INLINE void GIC_SetPendingIRQ ( IRQn_Type  IRQn)

Sets the given interrupt as pending using GIC's ISPENDR register.

Parameters
[in]IRQnThe interrupt to be enabled.

Adds the pending state to the corresponding interrupt.

◆ GIC_SetPriority()

__STATIC_INLINE void GIC_SetPriority ( IRQn_Type  IRQn,
uint32_t  priority 
)

Set the priority for the given interrupt in the GIC's IPRIORITYR register.

Parameters
[in]IRQnThe interrupt to be configured.
[in]priorityThe priority for the interrupt, lower values denote higher priorities.

Configures the priority of the given interrupt.

The available interrupt priorities are IMPLEMENTATION DEFINED. In order to query the actual priorities one can

GIC_SetPriority(IRQn_TIM1, UINT32_MAX); // try to configure lowest possible priority
uint32_t actual = GIC_GetPriority(IRQn_TIM1); // retrieve actual lowest priority usable
__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set the priority for the given interrupt in the GIC's IPRIORITYR register.
Definition: core_ca.h:1655
__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
Read the current interrupt priority from GIC's IPRIORITYR register.
Definition: core_ca.h:1664

◆ GIC_SetTarget()

__STATIC_INLINE void GIC_SetTarget ( IRQn_Type  IRQn,
uint32_t  cpu_target 
)

Sets the GIC's ITARGETSR register for the given interrupt.

Parameters
[in]IRQnInterrupt to be configured.
[in]cpu_targetCPU interfaces to assign this interrupt to.

The ITARGETSR registers provide an 8-bit CPU targets field for each interrupt supported by the GIC. This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority.