CMSIS-Core (Cortex-A)  
CMSIS-Core support for Cortex-A processor-based devices
 
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Peripheral Access

Naming conventions and optional features for accessing peripherals. More...

Macros

#define _VAL2FLD(field, value)
 Mask and shift a bit field value for assigning the result to a peripheral register.
 
#define _FLD2VAL(field, value)
 Extract from a peripheral register value the a bit field value.
 

Description

Naming conventions and optional features for accessing peripherals.

The section below describes the naming conventions, requirements, and optional features for accessing device specific peripherals. Most of the rules also apply to the core peripherals. The Device Header File <device.h> contains typically these definition and also includes the core specific header files.

The definitions for Peripheral Access can be generated using the CMSIS-SVD System View Description for Peripherals.

Each peripheral provides a data type definition with a name that is composed of:

Examples:

The data type definition uses standard C data types defined by the ANSI C header file <stdint.h>.

The typedef <device abbreviation>_UART_TypeDef shown below defines the generic register layout for all UART channels in a device.

typedef struct {
__O uint32_t UART_CR; // Offset: 0x0000 ( /W) Control Register
__IO uint32_t UART_MR; // Offset: 0x0004 (R/W) Mode Register
__O uint32_t UART_IER; // Offset: 0x0008 ( /W) Interrupt Enable Register
__O uint32_t UART_IDR; // Offset: 0x000C ( /W) Interrupt Disable Register
__I uint32_t UART_IMR; // Offset: 0x0010 (R/ ) Interrupt Mask Register
__I uint32_t UART_SR; // Offset: 0x0014 (R/ ) Status Register
__I uint32_t UART_RHR; // Offset: 0x0018 (R/ ) Receive Holding Register
__O uint32_t UART_THR; // Offset: 0x001C ( /W) Transmit Holding Register
__IO uint32_t UART_BRGR; // Offset: 0x0020 (R/W) Baud Rate Generator Register
__IO uint32_t UART_CMPR; // Offset: 0x0024 (R/W) Comparison Register
__IO uint32_t UART_RTOR; // Offset: 0x0028 (R/W) Receiver Time-out Register
__I uint32_t RESERVED[46]; // Offset: 0x002C (R/ ) Reserved
__IO uint32_t UART_WPMR; // Offset: 0x00E4 (R/W) Write Protection Mode Register
} IMX_UART_TypeDef;
#define __O
Defines 'write only' permissions.
Definition: core_ca.h:174
#define __IO
Defines 'read / write' permissions.
Definition: core_ca.h:175
#define __I
Defines 'read only' permissions.
Definition: core_ca.h:170
#define RESERVED(N, T)
Definition: core_ca.h:181

To access the registers of the UART defined above, pointers to this register structure are defined. If more instances of a peripheral exist, the variables have a postfix (digit or letter) that identifies the peripheral.

Example: In this example, IMX_UART2 and IMX_UART3 are two pointers to UARTs defined with above register structure.

#define IMX_UART2 ((IMX_UART_TypeDef *) IMX_UART2_BASE)
#define IMX_UART3 ((IMX_UART_TypeDef *) IMX_UART3_BASE)
Note
  • The prefix IMX is optional.

The registers in the various UARTs can now be referred in the user code as shown below:

val = IMX_UART2->SR // is the Status Register of UART2.

Minimal Requirements

To access the peripheral registers and related function in a device, the files device.h and core_ca.h define as a minimum:

These definitions allow accessing peripheral registers with simple assignments.


Optional Features

Optionally, the file device.h may define:


Register Bit Fields

For Core Register, macros define the position and the mask value for a bit field.

Example:

Bit field definitions for register ACTLR in CP15.

// CP15 Register ACTLR
#define ACTLR_DDI_Pos 28U
#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos)
#define ACTLR_DDVM_Pos 15U
#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos)
#define ACTLR_L1PCTL_Pos 13U
#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos)
#define ACTLR_L1RADIS_Pos 12U
#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos)
#define ACTLR_L2RADIS_Pos 11U
#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos)
#define ACTLR_DODMBS_Pos 10U
#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos)
#define ACTLR_SMP_Pos 6U
#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos)

The macros _VAL2FLD(field, value) and _FLD2VAL(field, value) enable access to bit fields.

Macro Definition Documentation

◆ _FLD2VAL

#define _FLD2VAL (   field,
  value 
)

Extract from a peripheral register value the a bit field value.

Parameters
fieldname of bit field.
valuevalue of the register. This parameter is interpreted as an uint32_t type.

The macro _FLD2VAL uses the #define's _Pos and _Msk of the related bit field to extract the value of a bit field from a register.

Example:

i = _FLD2VAL(ACTLR_SMP, ACTLR);
#define _FLD2VAL(field, value)
Mask and shift a register value to extract a bit filed value.
Definition: core_ca.h:674

◆ _VAL2FLD

#define _VAL2FLD (   field,
  value 
)

Mask and shift a bit field value for assigning the result to a peripheral register.

Parameters
fieldname of bit field.
valuevalue for the bit field. This parameter is interpreted as an uint32_t type.

The macro _VAL2FLD uses the #define's _Pos and _Msk of the related bit field to shift bit-field values for assigning to a register.

Example:

ACTLR = _VAL2FLD(ACTLR_SMP, 0x1)
#define _VAL2FLD(field, value)
Mask and shift a bit field value for use in a register bit range.
Definition: core_ca.h:666