Functions that relate to the Memory Protection Unit. More...
Data Structures | |
struct | ARM_MPU_Region_t |
Setup information of a single MPU Region. More... | |
Macros | |
#define | ARM_MPU_ATTR_DEVICE ( 0U ) |
Attribute for device memory (outer only) | |
#define | ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) |
Attribute for non-cacheable, normal memory. | |
#define | ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) |
Attribute for Normal memory, Outer and Inner cacheability. | |
#define | ARM_MPU_ATTR_DEVICE_nGnRnE |
Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement. | |
#define | ARM_MPU_ATTR_DEVICE_nGnRE |
Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement. | |
#define | ARM_MPU_ATTR_DEVICE_nGRE |
Device memory type non Gathering, Re-ordering, Early Write Acknowledgement. | |
#define | ARM_MPU_ATTR_DEVICE_GRE |
Device memory type Gathering, Re-ordering, Early Write Acknowledgement. | |
#define | MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE |
Normal memory outer-cacheable and inner-cacheable attributes WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate. | |
#define | MPU_ATTR_NORMAL_OUTER_WT_TR_RA |
#define | MPU_ATTR_NORMAL_OUTER_WT_TR_WA |
#define | MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA |
#define | MPU_ATTR_NORMAL_OUTER_WT_RA |
#define | MPU_ATTR_NORMAL_OUTER_WT_WA |
#define | MPU_ATTR_NORMAL_OUTER_WT_RA_WA |
#define | MPU_ATTR_NORMAL_OUTER_WB_TR_RA |
#define | MPU_ATTR_NORMAL_OUTER_WB_TR_WA |
#define | MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA |
#define | MPU_ATTR_NORMAL_OUTER_WB_RA |
#define | MPU_ATTR_NORMAL_OUTER_WB_WA |
#define | MPU_ATTR_NORMAL_OUTER_WB_RA_WA |
#define | MPU_ATTR_NORMAL_INNER_NON_CACHEABLE |
#define | MPU_ATTR_NORMAL_INNER_WT_TR_RA |
#define | MPU_ATTR_NORMAL_INNER_WT_TR_WA |
#define | MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA |
#define | MPU_ATTR_NORMAL_INNER_WT_RA |
#define | MPU_ATTR_NORMAL_INNER_WT_WA |
#define | MPU_ATTR_NORMAL_INNER_WT_RA_WA |
#define | MPU_ATTR_NORMAL_INNER_WB_TR_RA |
#define | MPU_ATTR_NORMAL_INNER_WB_TR_WA |
#define | MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA |
#define | MPU_ATTR_NORMAL_INNER_WB_RA |
#define | MPU_ATTR_NORMAL_INNER_WB_WA |
#define | MPU_ATTR_NORMAL_INNER_WB_RA_WA |
#define | ARM_MPU_ATTR(O, I) |
Memory Attribute. | |
#define | ARM_MPU_SH_NON |
Normal memory non-shareable | |
#define | ARM_MPU_SH_OUTER |
Normal memory outer shareable | |
#define | ARM_MPU_SH_INNER |
Normal memory inner shareable | |
#define | ARM_MPU_AP_RW |
Normal memory, read/write. | |
#define | ARM_MPU_AP_RO |
Normal memory, read-only. | |
#define | ARM_MPU_AP_NP |
Normal memory, any privilege level. | |
#define | ARM_MPU_AP_PO |
Normal memory, privileged access only. | |
#define | ARM_MPU_XN |
Normal memory, Execution only permitted if read permitted. | |
#define | ARM_MPU_EX |
Normal memory, Execution only permitted if read permitted. | |
#define | ARM_MPU_AP_(RO, NP) |
Memory access permissions. | |
#define | ARM_MPU_RBAR(BASE, SH, RO, NP, XN) |
Region Base Address Register value. | |
#define | ARM_MPU_RLAR(LIMIT, IDX) |
Region Limit Address Register value. | |
#define | ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) |
Region Limit Address Register with PXN value. | |
Functions | |
__STATIC_INLINE uint32_t | ARM_MPU_TYPE () |
Read MPU Type Register. | |
__STATIC_INLINE void | ARM_MPU_Enable (uint32_t MPU_Control) |
Enable the MPU. | |
__STATIC_INLINE void | ARM_MPU_Disable (void) |
__STATIC_INLINE | ARM_MPU_Enable_NS (uint32_t MPU_Control) |
__STATIC_INLINE void | ARM_MPU_Disable_NS (void) |
__STATIC_INLINE void | ARM_MPU_SetMemAttrEx (MPU_Type *mpu, uint8_t idx, uint8_t attr) |
__STATIC_INLINE void | ARM_MPU_SetMemAttr (uint8_t idx, uint8_t attr) |
__STATIC_INLINE void | ARM_MPU_SetMemAttr_NS (uint8_t idx, uint8_t attr) |
__STATIC_INLINE void | ARM_MPU_ClrRegionEx (MPU_Type *mpu, uint32_t rnr) |
__STATIC_INLINE void | ARM_MPU_ClrRegion (uint32_t rnr) |
__STATIC_INLINE void | ARM_MPU_ClrRegion_NS (uint32_t rnr) |
__STATIC_INLINE void | ARM_MPU_SetRegionEx (MPU_Type *mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) |
__STATIC_INLINE void | ARM_MPU_SetRegion (uint32_t rnr, uint32_t rbar, uint32_t rlar) |
__STATIC_INLINE void | ARM_MPU_SetRegion_NS (uint32_t rnr, uint32_t rbar, uint32_t rlar) |
__STATIC_INLINE void | ARM_MPU_OrderedMemcpy (volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len) |
__STATIC_INLINE void | ARM_MPU_LoadEx (MPU_Type *mpu, uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt) |
__STATIC_INLINE void | ARM_MPU_Load (uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt) |
__STATIC_INLINE void | ARM_MPU_Load_NS (uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt) |
Functions that relate to the Memory Protection Unit.
The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M23, M33, M35P processor.
The MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.
Example:
#define ARM_MPU_AP_ | ( | RO, | |
NP | |||
) |
Memory access permissions.
RO | Read-Only: Set to 1 for read-only memory. |
NP | Non-Privileged: Set to 1 for non-privileged memory. |
#define ARM_MPU_AP_NP |
Normal memory, any privilege level.
#define ARM_MPU_AP_PO |
Normal memory, privileged access only.
#define ARM_MPU_AP_RO |
Normal memory, read-only.
#define ARM_MPU_AP_RW |
Normal memory, read/write.
Access permissions AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only
#define ARM_MPU_ATTR | ( | O, | |
I | |||
) |
Memory Attribute.
O | Outer memory attributes |
I | O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes |
#define ARM_MPU_ATTR_DEVICE ( 0U ) |
Attribute for device memory (outer only)
#define ARM_MPU_ATTR_DEVICE_GRE |
Device memory type Gathering, Re-ordering, Early Write Acknowledgement.
#define ARM_MPU_ATTR_DEVICE_nGnRE |
Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement.
#define ARM_MPU_ATTR_DEVICE_nGnRnE |
Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement.
#define ARM_MPU_ATTR_DEVICE_nGRE |
Device memory type non Gathering, Re-ordering, Early Write Acknowledgement.
#define ARM_MPU_ATTR_MEMORY_ | ( | NT, | |
WB, | |||
RA, | |||
WA | |||
) |
Attribute for Normal memory, Outer and Inner cacheability.
NT | Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data. |
WB | Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy. |
RA | Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss. |
WA | Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss. |
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) |
Attribute for non-cacheable, normal memory.
#define ARM_MPU_EX |
Normal memory, Execution only permitted if read permitted.
#define ARM_MPU_RBAR | ( | BASE, | |
SH, | |||
RO, | |||
NP, | |||
XN | |||
) |
Region Base Address Register value.
BASE | The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. |
SH | Defines the Shareability domain for this memory region. |
RO | Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region. |
NP | Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region. |
XN | eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region. |
#define ARM_MPU_RLAR | ( | LIMIT, | |
IDX | |||
) |
Region Limit Address Register value.
LIMIT | The limit address bits [31:5] for this memory region. The value is one extended. |
IDX | The attribute index to be associated with this memory region. |
#define ARM_MPU_RLAR_PXN | ( | LIMIT, | |
PXN, | |||
IDX | |||
) |
Region Limit Address Register with PXN value.
LIMIT | The limit address bits [31:5] for this memory region. The value is one extended. |
PXN | Privileged execute never. Defines whether code can be executed from this privileged region. |
IDX | The attribute index to be associated with this memory region. |
#define ARM_MPU_SH_INNER |
Normal memory inner shareable
#define ARM_MPU_SH_NON |
Normal memory non-shareable
Shareability
#define ARM_MPU_SH_OUTER |
Normal memory outer shareable
#define ARM_MPU_XN |
Normal memory, Execution only permitted if read permitted.
#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE |
#define MPU_ATTR_NORMAL_INNER_WB_RA |
#define MPU_ATTR_NORMAL_INNER_WB_RA_WA |
#define MPU_ATTR_NORMAL_INNER_WB_TR_RA |
#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA |
#define MPU_ATTR_NORMAL_INNER_WB_TR_WA |
#define MPU_ATTR_NORMAL_INNER_WB_WA |
#define MPU_ATTR_NORMAL_INNER_WT_RA |
#define MPU_ATTR_NORMAL_INNER_WT_RA_WA |
#define MPU_ATTR_NORMAL_INNER_WT_TR_RA |
#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA |
#define MPU_ATTR_NORMAL_INNER_WT_TR_WA |
#define MPU_ATTR_NORMAL_INNER_WT_WA |
#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE |
Normal memory outer-cacheable and inner-cacheable attributes WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate.
#define MPU_ATTR_NORMAL_OUTER_WB_RA |
#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA |
#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA |
#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA |
#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA |
#define MPU_ATTR_NORMAL_OUTER_WB_WA |
#define MPU_ATTR_NORMAL_OUTER_WT_RA |
#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA |
#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA |
#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA |
#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA |
#define MPU_ATTR_NORMAL_OUTER_WT_WA |
__STATIC_INLINE void ARM_MPU_ClrRegion | ( | uint32_t | rnr | ) |
Clear and disable the given MPU region.
rnr | Region number to be cleared. |
__STATIC_INLINE void ARM_MPU_ClrRegion_NS | ( | uint32_t | rnr | ) |
Clear and disable the given Non-secure MPU region.
rnr | Region number to be cleared. |
__STATIC_INLINE void ARM_MPU_ClrRegionEx | ( | MPU_Type * | mpu, |
uint32_t | rnr | ||
) |
Clear and disable the given MPU region of the given MPU.
mpu | Pointer to MPU to be used. |
rnr | Region number to be cleared. |
__STATIC_INLINE void ARM_MPU_Disable | ( | void | ) |
Disable the MPU.
__STATIC_INLINE void ARM_MPU_Disable_NS | ( | void | ) |
Disable the Non-secure MPU.
__STATIC_INLINE void ARM_MPU_Enable | ( | uint32_t | MPU_Control | ) |
Enable the MPU.
MPU_Control | Default access permissions for unconfigured regions. |
__STATIC_INLINE ARM_MPU_Enable_NS | ( | uint32_t | MPU_Control | ) |
Enable the Non-secure MPU.
MPU_Control | Default access permissions for unconfigured regions. |
__STATIC_INLINE void ARM_MPU_Load | ( | uint32_t | rnr, |
ARM_MPU_Region_t const * | table, | ||
uint32_t | cnt | ||
) |
Load the given number of MPU regions from a table.
rnr | First region number to be configured. |
table | Pointer to the MPU configuration table. |
cnt | Amount of regions to be configured. |
Example:
__STATIC_INLINE void ARM_MPU_Load_NS | ( | uint32_t | rnr, |
ARM_MPU_Region_t const * | table, | ||
uint32_t | cnt | ||
) |
Load the given number of MPU regions from a table to the Non-secure MPU.
rnr | First region number to be configured. |
table | Pointer to the MPU configuration table. |
cnt | Amount of regions to be configured. |
__STATIC_INLINE void ARM_MPU_LoadEx | ( | MPU_Type * | mpu, |
uint32_t | rnr, | ||
ARM_MPU_Region_t const * | table, | ||
uint32_t | cnt | ||
) |
Load the given number of MPU regions from a table to the given MPU.
mpu | Pointer to the MPU registers to be used. |
rnr | First region number to be configured. |
table | Pointer to the MPU configuration table. |
cnt | Amount of regions to be configured. |
__STATIC_INLINE void ARM_MPU_OrderedMemcpy | ( | volatile uint32_t * | dst, |
const uint32_t *__RESTRICT | src, | ||
uint32_t | len | ||
) |
Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx.
dst | Destination data is copied to. |
src | Source data is copied from. |
len | Amount of data words to be copied. |
__STATIC_INLINE void ARM_MPU_SetMemAttr | ( | uint8_t | idx, |
uint8_t | attr | ||
) |
Set the memory attribute encoding.
idx | The attribute index to be set [0-7] |
attr | The attribute value to be set. |
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS | ( | uint8_t | idx, |
uint8_t | attr | ||
) |
Set the memory attribute encoding to the Non-secure MPU.
idx | The attribute index to be set [0-7] |
attr | The attribute value to be set. |
__STATIC_INLINE void ARM_MPU_SetMemAttrEx | ( | MPU_Type * | mpu, |
uint8_t | idx, | ||
uint8_t | attr | ||
) |
Set the memory attribute encoding to the given MPU.
mpu | Pointer to the MPU to be configured. |
idx | The attribute index to be set [0-7] |
attr | The attribute value to be set. |
__STATIC_INLINE void ARM_MPU_SetRegion | ( | uint32_t | rnr, |
uint32_t | rbar, | ||
uint32_t | rlar | ||
) |
Configure the given MPU region.
rnr | Region number to be configured. |
rbar | Value for RBAR register. |
rlar | Value for RLAR register. |
__STATIC_INLINE void ARM_MPU_SetRegion_NS | ( | uint32_t | rnr, |
uint32_t | rbar, | ||
uint32_t | rlar | ||
) |
Configure the given Non-secure MPU region.
rnr | Region number to be configured. |
rbar | Value for RBAR register. |
rlar | Value for RLAR register. |
__STATIC_INLINE void ARM_MPU_SetRegionEx | ( | MPU_Type * | mpu, |
uint32_t | rnr, | ||
uint32_t | rbar, | ||
uint32_t | rlar | ||
) |
Configure the given MPU region of the given MPU.
mpu | Pointer to MPU to be used. |
rnr | Region number to be configured. |
rbar | Value for RBAR register. |
rlar | Value for RLAR register. |
__STATIC_INLINE uint32_t ARM_MPU_TYPE | ( | ) |
Read MPU Type Register.