CMSIS-Core (Cortex-M)
Version 5.6.0
CMSIS-Core support for Cortex-M processor-based devices
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Functions for the level-1 instruction cache. More...
Functions | |
__STATIC_FORCEINLINE void | SCB_EnableICache (void) |
Enable I-Cache. More... | |
__STATIC_FORCEINLINE void | SCB_DisableICache (void) |
Disable I-Cache. More... | |
__STATIC_FORCEINLINE void | SCB_InvalidateICache (void) |
Invalidate I-Cache. More... | |
__STATIC_FORCEINLINE void | SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) |
I-Cache Invalidate by address. More... | |
Functions for the level-1 instruction cache.
__STATIC_FORCEINLINE void SCB_DisableICache | ( | void | ) |
Disable I-Cache.
The function turns off the instruction cache.
__STATIC_FORCEINLINE void SCB_EnableICache | ( | void | ) |
Enable I-Cache.
The function turns on the instruction cache.
__STATIC_FORCEINLINE void SCB_InvalidateICache | ( | void | ) |
Invalidate I-Cache.
The function invalidates the instruction cache. The instruction cache is never dirty so cache RAM errors are always recoverable by invalidating the cache and retrying the instruction.
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr | ( | volatile void * | addr, |
int32_t | isize | ||
) |
I-Cache Invalidate by address.
Invalidates I-Cache for the given address. I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. I-Cache memory blocks which are part of given address + given size are invalidated.
[in] | addr | address |
[in] | isize | size of memory block (in number of bytes) |