CMSIS-Core (Cortex-M)  Version 5.4.0
CMSIS-Core support for Cortex-M processor-based devices
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MPU Functions for Armv8-M

Functions that relate to the Memory Protection Unit. More...

Data Structures

struct  ARM_MPU_Region_t
 Setup information of a single MPU Region. More...
 

Macros

#define ARM_MPU_ATTR_DEVICE   ( 0U )
 Attribute for device memory (outer only) More...
 
#define ARM_MPU_ATTR_NON_CACHEABLE   ( 4U )
 Attribute for non-cacheable, normal memory. More...
 
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA)
 Attribute for normal memory (outer and inner) More...
 
#define ARM_MPU_ATTR_DEVICE_nGnRnE
 Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement. More...
 
#define ARM_MPU_ATTR_DEVICE_nGnRE
 Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement. More...
 
#define ARM_MPU_ATTR_DEVICE_nGRE
 Device memory type non Gathering, Re-ordering, Early Write Acknowledgement. More...
 
#define ARM_MPU_ATTR_DEVICE_GRE
 Device memory type Gathering, Re-ordering, Early Write Acknowledgement. More...
 
#define ARM_MPU_ATTR(O, I)
 Memory Attribute. More...
 
#define ARM_MPU_SH_NON
 Normal memory non-shareable. More...
 
#define ARM_MPU_SH_OUTER
 Normal memory outer shareable. More...
 
#define ARM_MPU_SH_INNER
 Normal memory inner shareable. More...
 
#define ARM_MPU_AP_(RO, NP)
 Memory access permissions. More...
 
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN)
 Region Base Address Register value. More...
 
#define ARM_MPU_RLAR(LIMIT, IDX)
 Region Limit Address Register value. More...
 

Functions

__STATIC_INLINE void ARM_MPU_Enable (uint32_t MPU_Control)
 
__STATIC_INLINE void ARM_MPU_Disable (void)
 
__STATIC_INLINE ARM_MPU_Enable_NS (uint32_t MPU_Control)
 
__STATIC_INLINE void ARM_MPU_Disable_NS (void)
 
__STATIC_INLINE void ARM_MPU_SetMemAttrEx (MPU_Type *mpu, uint8_t idx, uint8_t attr)
 
__STATIC_INLINE void ARM_MPU_SetMemAttr (uint8_t idx, uint8_t attr)
 
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS (uint8_t idx, uint8_t attr)
 
__STATIC_INLINE void ARM_MPU_ClrRegionEx (MPU_Type *mpu, uint32_t rnr)
 
__STATIC_INLINE void ARM_MPU_ClrRegion (uint32_t rnr)
 
__STATIC_INLINE void ARM_MPU_ClrRegion_NS (uint32_t rnr)
 
__STATIC_INLINE void ARM_MPU_SetRegionEx (MPU_Type *mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
 
__STATIC_INLINE void ARM_MPU_SetRegion (uint32_t rnr, uint32_t rbar, uint32_t rlar)
 
__STATIC_INLINE void ARM_MPU_SetRegion_NS (uint32_t rnr, uint32_t rbar, uint32_t rlar)
 
__STATIC_INLINE void ARM_MPU_OrderedMemcpy (volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)
 
__STATIC_INLINE void ARM_MPU_LoadEx (MPU_Type *mpu, uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)
 
__STATIC_INLINE void ARM_MPU_Load (uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)
 
__STATIC_INLINE void ARM_MPU_Load_NS (uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)
 

Description

Functions that relate to the Memory Protection Unit.

The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M23, M33, M35P processor.

The MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.

Example:

void main()
{
// Set Region 0 using Attr 0
ARM_MPU_SetMemAttr(0UL, ARM_MPU_ATTR( /* Normal memory */
ARM_MPU_ATTR_MEMORY_(0UL, 1UL, 1UL, 1UL), /* Outer Write-Back transient with read and write allocate */
ARM_MPU_ATTR_MEMORY_(0UL, 0UL, 1UL, 1UL) /* Inner Write-Through transient with read and write allocate */
));
ARM_MPU_RBAR(0x08000000UL, ARM_MPU_SH_NON, 0UL, 1UL, 1UL), /* Non-shareable, read/write, non-privileged, execute-never */
ARM_MPU_RLAR(0x080FFFFFUL, 0UL) /* 1MB memory block using Attr 0 */
);
// Execute application code that is access protected by the MPU
}

Macro Definition Documentation

#define ARM_MPU_AP_ (   RO,
  NP 
)

Memory access permissions.

Parameters
RORead-Only: Set to 1 for read-only memory.
NPNon-Privileged: Set to 1 for non-privileged memory.
#define ARM_MPU_ATTR (   O,
 
)

Memory Attribute.

Parameters
OOuter memory attributes
IO == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
#define ARM_MPU_ATTR_DEVICE   ( 0U )

Attribute for device memory (outer only)

#define ARM_MPU_ATTR_DEVICE_GRE

Device memory type Gathering, Re-ordering, Early Write Acknowledgement.

#define ARM_MPU_ATTR_DEVICE_nGnRE

Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement.

#define ARM_MPU_ATTR_DEVICE_nGnRnE

Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement.

#define ARM_MPU_ATTR_DEVICE_nGRE

Device memory type non Gathering, Re-ordering, Early Write Acknowledgement.

#define ARM_MPU_ATTR_MEMORY_ (   NT,
  WB,
  RA,
  WA 
)

Attribute for normal memory (outer and inner)

Parameters
NTNon-Transient: Set to 1 for non-transient data.
WBWrite-Back: Set to 1 to use write-back update policy.
RARead Allocation: Set to 1 to use cache allocation on read miss.
WAWrite Allocation: Set to 1 to use cache allocation on write miss.
#define ARM_MPU_ATTR_NON_CACHEABLE   ( 4U )

Attribute for non-cacheable, normal memory.

#define ARM_MPU_RBAR (   BASE,
  SH,
  RO,
  NP,
  XN 
)

Region Base Address Register value.

Parameters
BASEThe base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
SHDefines the Shareability domain for this memory region.
RORead-Only: Set to 1 for a read-only memory region.
NPNon-Privileged: Set to 1 for a non-privileged memory region.
XNeXecute Never: Set to 1 for a non-executable memory region.
#define ARM_MPU_RLAR (   LIMIT,
  IDX 
)

Region Limit Address Register value.

Parameters
LIMITThe limit address bits [31:5] for this memory region. The value is one extended.
IDXThe attribute index to be associated with this memory region.
#define ARM_MPU_SH_INNER

Normal memory inner shareable.

#define ARM_MPU_SH_NON

Normal memory non-shareable.

#define ARM_MPU_SH_OUTER

Normal memory outer shareable.

Function Documentation

__STATIC_INLINE void ARM_MPU_ClrRegion ( uint32_t  rnr)

Clear and disable the given MPU region.

Parameters
rnrRegion number to be cleared.
__STATIC_INLINE void ARM_MPU_ClrRegion_NS ( uint32_t  rnr)

Clear and disable the given Non-secure MPU region.

Parameters
rnrRegion number to be cleared.
__STATIC_INLINE void ARM_MPU_ClrRegionEx ( MPU_Type mpu,
uint32_t  rnr 
)

Clear and disable the given MPU region of the given MPU.

Parameters
mpuPointer to MPU to be used.
rnrRegion number to be cleared.
__STATIC_INLINE void ARM_MPU_Disable ( void  )

Disable the MPU.

__STATIC_INLINE void ARM_MPU_Disable_NS ( void  )

Disable the Non-secure MPU.

__STATIC_INLINE void ARM_MPU_Enable ( uint32_t  MPU_Control)

Enable the MPU.

Parameters
MPU_ControlDefault access permissions for unconfigured regions.
__STATIC_INLINE ARM_MPU_Enable_NS ( uint32_t  MPU_Control)

Enable the Non-secure MPU.

Parameters
MPU_ControlDefault access permissions for unconfigured regions.
__STATIC_INLINE void ARM_MPU_Load ( uint32_t  rnr,
ARM_MPU_Region_t const *  table,
uint32_t  cnt 
)

Load the given number of MPU regions from a table.

Parameters
rnrFirst region number to be configured.
tablePointer to the MPU configuration table.
cntAmount of regions to be configured.

Example:

const ARM_MPU_Region_t mpuTable[1][4] = {
{
// BASE SH RO NP XN LIMIT ATTR
{ .RBAR = ARM_MPU_RBAR(0x08000000UL, ARM_MPU_SH_NON, 0UL, 1UL, 0UL), .RLAR = ARM_MPU_RLAR(0x080FFFFFUL, 0UL) },
{ .RBAR = ARM_MPU_RBAR(0x20000000UL, ARM_MPU_SH_NON, 0UL, 1UL, 1UL), .RLAR = ARM_MPU_RLAR(0x20007FFFUL, 0UL) },
{ .RBAR = ARM_MPU_RBAR(0x40020000UL, ARM_MPU_SH_NON, 0UL, 1UL, 1UL), .RLAR = ARM_MPU_RLAR(0x40021FFFUL, 1UL) },
{ .RBAR = ARM_MPU_RBAR(0x40022000UL, ARM_MPU_SH_NON, 0UL, 1UL, 1UL), .RLAR = ARM_MPU_RLAR(0x40022FFFUL, 1UL) }
}
};
void UpdateMpu(uint32_t idx)
{
ARM_MPU_Load(0, mpuTable[idx], 4);
}
__STATIC_INLINE void ARM_MPU_Load_NS ( uint32_t  rnr,
ARM_MPU_Region_t const *  table,
uint32_t  cnt 
)

Load the given number of MPU regions from a table to the Non-secure MPU.

Parameters
rnrFirst region number to be configured.
tablePointer to the MPU configuration table.
cntAmount of regions to be configured.
__STATIC_INLINE void ARM_MPU_LoadEx ( MPU_Type mpu,
uint32_t  rnr,
ARM_MPU_Region_t const *  table,
uint32_t  cnt 
)

Load the given number of MPU regions from a table to the given MPU.

Parameters
mpuPointer to the MPU registers to be used.
rnrFirst region number to be configured.
tablePointer to the MPU configuration table.
cntAmount of regions to be configured.
__STATIC_INLINE void ARM_MPU_OrderedMemcpy ( volatile uint32_t *  dst,
const uint32_t *__RESTRICT  src,
uint32_t  len 
)

Memcopy with strictly ordered memory access, e.g. for register targets.

Parameters
dstDestination data is copied to.
srcSource data is copied from.
lenAmount of data words to be copied.
__STATIC_INLINE void ARM_MPU_SetMemAttr ( uint8_t  idx,
uint8_t  attr 
)

Set the memory attribute encoding.

Parameters
idxThe attribute index to be set [0-7]
attrThe attribute value to be set.
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS ( uint8_t  idx,
uint8_t  attr 
)

Set the memory attribute encoding to the Non-secure MPU.

Parameters
idxThe attribute index to be set [0-7]
attrThe attribute value to be set.
__STATIC_INLINE void ARM_MPU_SetMemAttrEx ( MPU_Type mpu,
uint8_t  idx,
uint8_t  attr 
)

Set the memory attribute encoding to the given MPU.

Parameters
mpuPointer to the MPU to be configured.
idxThe attribute index to be set [0-7]
attrThe attribute value to be set.
__STATIC_INLINE void ARM_MPU_SetRegion ( uint32_t  rnr,
uint32_t  rbar,
uint32_t  rlar 
)

Configure the given MPU region.

Parameters
rnrRegion number to be configured.
rbarValue for RBAR register.
rlarValue for RLAR register.
__STATIC_INLINE void ARM_MPU_SetRegion_NS ( uint32_t  rnr,
uint32_t  rbar,
uint32_t  rlar 
)

Configure the given Non-secure MPU region.

Parameters
rnrRegion number to be configured.
rbarValue for RBAR register.
rlarValue for RLAR register.
__STATIC_INLINE void ARM_MPU_SetRegionEx ( MPU_Type mpu,
uint32_t  rnr,
uint32_t  rbar,
uint32_t  rlar 
)

Configure the given MPU region of the given MPU.

Parameters
mpuPointer to MPU to be used.
rnrRegion number to be configured.
rbarValue for RBAR register.
rlarValue for RLAR register.