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CMSIS-Core (Cortex-A)
Version 1.2.1
CMSIS-Core support for Cortex-A processor-based devices
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![]() ![]() | Bit field declaration for ACTLR layout |
![]() ![]() | Physical Timer Control register |
![]() ![]() | Bit field declaration for CPACR layout |
![]() ![]() | Bit field declaration for CPSR layout |
![]() ![]() | Bit field declaration for DFSR layout |
![]() ![]() | Bit field declaration for FPSCR layout |
![]() ![]() | Structure type to access the Generic Interrupt Controller Distributor (GICD) |
![]() ![]() | Structure type to access the Generic Interrupt Controller Interface (GICC) |
![]() ![]() | Bit field declaration for IFSR layout |
![]() ![]() | Bit field declaration for ISR layout |
![]() ![]() | Union type to access the L2C_310 Cache Controller |
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![]() ![]() | Bit field declaration for SCTLR layout |
![]() ![]() | Structure type to access the Private Timer |