VSI API

Virtual Streaming Interface API for application firmware. More...

Data Structures
struct	ARM_VSI_Type
	Structure type to access the virtual streaming interface. More...
struct	ARM_VSI_Type.IRQ
	Interrupt Request (IRQ) More...
struct	ARM_VSI_Type.Timer
	Time counter with 1MHz input frequency. More...
struct	ARM_VSI_Type.DMA
	Direct Memory Access (DMA) Controller. More...

Macros
#define	ARM_VSI0_BASE   (0x4FF00000UL)
#define	ARM_VSI1_BASE   (0x4FF10000UL)
#define	ARM_VSI2_BASE   (0x4FF20000UL)
#define	ARM_VSI3_BASE   (0x4FF30000UL)
#define	ARM_VSI4_BASE   (0x4FF40000UL)
#define	ARM_VSI5_BASE   (0x4FF50000UL)
#define	ARM_VSI6_BASE   (0x4FF60000UL)
#define	ARM_VSI7_BASE   (0x4FF70000UL)
#define	ARM_VSI0   ((ARM_VSI_Type *)ARM_VSI0_BASE)
#define	ARM_VSI1   ((ARM_VSI_Type *)ARM_VSI1_BASE)
#define	ARM_VSI2   ((ARM_VSI_Type *)ARM_VSI2_BASE)
#define	ARM_VSI3   ((ARM_VSI_Type *)ARM_VSI3_BASE)
#define	ARM_VSI4   ((ARM_VSI_Type *)ARM_VSI4_BASE)
#define	ARM_VSI5   ((ARM_VSI_Type *)ARM_VSI5_BASE)
#define	ARM_VSI6   ((ARM_VSI_Type *)ARM_VSI6_BASE)
#define	ARM_VSI7   ((ARM_VSI_Type *)ARM_VSI7_BASE)

Description

Virtual Streaming Interface API for application firmware.

The VSI peripheral is accessed using the ARM_VSI_Type structure that defines registers for the following components:

• Interrupt control
• Timer peripheral with 1MHz input clock
• DMA peripheral with block buffer handling
• 64 user registers to implement bespoke functionality (i.e. for Audio, Video, or Sensor streaming)

8 VSI peripheral instances are mapped into the memory of a Cortex-M system:

/* Memory mapping of 8 VSI peripherals */
#define ARM_VSI0_BASE           (0x4FF00000UL)                          /*!< VSI 0 Base Address */
#define ARM_VSI1_BASE           (0x4FF10000UL)                          /*!< VSI 1 Base Address */
#define ARM_VSI2_BASE           (0x4FF20000UL)                          /*!< VSI 2 Base Address */
#define ARM_VSI3_BASE           (0x4FF30000UL)                          /*!< VSI 3 Base Address */
#define ARM_VSI4_BASE           (0x4FF40000UL)                          /*!< VSI 4 Base Address */
#define ARM_VSI5_BASE           (0x4FF50000UL)                          /*!< VSI 5 Base Address */
#define ARM_VSI6_BASE           (0x4FF60000UL)                          /*!< VSI 6 Base Address */
#define ARM_VSI7_BASE           (0x4FF70000UL)                          /*!< VSI 7 Base Address */
#define ARM_VSI0                ((ARM_VSI_Type *)ARM_VSI0_BASE)         /*!< VSI 0 struct */
#define ARM_VSI1                ((ARM_VSI_Type *)ARM_VSI1_BASE)         /*!< VSI 1 struct */
#define ARM_VSI2                ((ARM_VSI_Type *)ARM_VSI2_BASE)         /*!< VSI 2 struct */
#define ARM_VSI3                ((ARM_VSI_Type *)ARM_VSI3_BASE)         /*!< VSI 3 struct */
#define ARM_VSI4                ((ARM_VSI_Type *)ARM_VSI4_BASE)         /*!< VSI 4 struct */
#define ARM_VSI5                ((ARM_VSI_Type *)ARM_VSI5_BASE)         /*!< VSI 5 struct */
#define ARM_VSI6                ((ARM_VSI_Type *)ARM_VSI6_BASE)         /*!< VSI 6 struct */
#define ARM_VSI7                ((ARM_VSI_Type *)ARM_VSI7_BASE)         /*!< VSI 7 struct */

The ARM_VSI_Type structure is defined in arm_vsi.h file as follows:

/// Structure type to access the virtual streaming interface
typedef struct
{
  /// Interrupt Request (IRQ)
  struct {
    __IOM uint32_t Enable;      /*!< (R/W) IRQ Enable */
    __OM  uint32_t Set;         /*!< (-/W) IRQ Set */
    __OM  uint32_t Clear;       /*!< (-/W) IRQ Clear */
    __IM  uint32_t Status;      /*!< (R/-) IRQ Status */
  } IRQ;
  uint32_t reserved1[60];
 
  /// Time counter with 1MHz input frequency
  struct {
    __IOM uint32_t Control;     /*!< (R/W) Timer Control */
    __IOM uint32_t Interval;    /*!< (R/W) Timer Interval Value (in microseconds) */
    __IM  uint32_t Count;       /*!< (R/-) Timer Overflow Count */
  } Timer;
  uint32_t reserved2[61];
 
  /// Direct Memory Access (DMA) Controller
  struct {
    __IOM uint32_t Control;     /*!< (R/W) DMA Control */
    __IOM uint32_t Address;     /*!< (R/W) DMA Memory Start Address */
    __IOM uint32_t BlockSize;   /*!< (R/W) DMA Block Size (in bytes, multiple of 4) */
    __IOM uint32_t BlockNum;    /*!< (R/W) DMA Number of Blocks (must be 2^n) */
    __IM  uint32_t BlockIndex;  /*!< (R/-) DMA Block Index */
  } DMA;
  uint32_t reserved3[59];
 
  __IOM uint32_t Regs[64];      /*!< (R/W) User Registers */
 
} ARM_VSI_Type;

The ARM_VSI_Type::IRQ peripheral simulates an interrupt request. Set and Clear parameters have only write access and are used for triggering and clearing the interrupt. Status field indicates the interrupt state.

The ARM_VSI_Type::Timer peripheral is a simple counting timer with a 1MHz input frequency based on the time domain of the Arm Fast Model instruction set simulator. The Count value increments when the Interval value elapses.

The ARM_VSI_Type::DMA controller accesses a rotating memory buffer as shown in the diagram below. Each block transfer increments the BlockIndex value (restarts when the buffer rotates).

Structure of DMA memory buffer

---

Data Structure Documentation

ARM_VSI_Type

struct ARM_VSI_Type

Structure type to access the virtual streaming interface.

The ARM_VSI_Type structure provides access to the VSI peripheral registers. The peripheral provides the following registers:

Data Fields
struct ARM_VSI_Type.IRQ	IRQ	Interrupt Request (IRQ) A group of registers that can enable and set/clear interrupt requests.
uint32_t	reserved1[60]
struct ARM_VSI_Type.Timer	Timer	Time counter with 1MHz input frequency. A simple counting timer with a 1MHz input frequency based on the time domain of the Arm Fast Model instruction set simulator. The Timer peripheral has the following registers: Control the operation of the timer with the following control bits: Control.0 0=stop timer and timer reset, 1=start timer Control.1 0=on-shoot timer, 1=periodic timer by reloading Interval value Control.2 0=no interrupt, 1=trigger interrupt at overflow, sets IRQ.Status=1 Control.3 0=no DMA transfer, 1=trigger DMA transfer at overflow Interval value in microseconds for timer overflows Count timer overflow counter, incremented when the time interval elapses and reset to 0 when timer starts.
uint32_t	reserved2[61]
struct ARM_VSI_Type.DMA	DMA	Direct Memory Access (DMA) Controller. A virtual DMA controller which copies data from/to peripheral to/from memory. It has the following registers: Control the operation of the DMA with the following control bits: Control.0 0=disable DMA and reset DMA, 1=enable DMA Control.1 DMA transfer direction 0=peripheral to memory, 1=memory to peripheral Address start address of the memory region BlockSize number of bytes for each DMA transfer. BlockNum number of blocks before the memory buffer rotates, next DMA transfer uses start address. BlockIndex counts the total number of blocks transferred. It gets set to 0 when DMA is enabled and also when buffer rotates.
uint32_t	reserved3[59]
__IOM uint32_t	Regs[64]	(R/W) User Registers Array of registers that allows to implement peripheral specific operations.

ARM_VSI_Type.IRQ

struct ARM_VSI_Type.IRQ

Interrupt Request (IRQ)

Data Fields
__IOM uint32_t	Enable	(R/W) IRQ Enable
__OM uint32_t	Set	(-/W) IRQ Set
__OM uint32_t	Clear	(-/W) IRQ Clear
__IM uint32_t	Status	(R/-) IRQ Status

ARM_VSI_Type.Timer

struct ARM_VSI_Type.Timer

Time counter with 1MHz input frequency.

Data Fields
__IOM uint32_t	Control	(R/W) Timer Control
__IOM uint32_t	Interval	(R/W) Timer Interval Value (in microseconds)
__IM uint32_t	Count	(R/-) Timer Overflow Count

ARM_VSI_Type.DMA

struct ARM_VSI_Type.DMA

Direct Memory Access (DMA) Controller.

Data Fields
__IOM uint32_t	Control	(R/W) DMA Control
__IOM uint32_t	Address	(R/W) DMA Memory Start Address
__IOM uint32_t	BlockSize	(R/W) DMA Block Size (in bytes, multiple of 4)
__IOM uint32_t	BlockNum	(R/W) DMA Number of Blocks (must be 2^n)
__IM uint32_t	BlockIndex	(R/-) DMA Block Index

Macro Definition Documentation

ARM_VSI0_BASE

#define ARM_VSI0_BASE   (0x4FF00000UL)

VSI 0 Base Address

ARM_VSI1_BASE

#define ARM_VSI1_BASE   (0x4FF10000UL)

VSI 1 Base Address

ARM_VSI2_BASE

#define ARM_VSI2_BASE   (0x4FF20000UL)

VSI 2 Base Address

ARM_VSI3_BASE

#define ARM_VSI3_BASE   (0x4FF30000UL)

VSI 3 Base Address

ARM_VSI4_BASE

#define ARM_VSI4_BASE   (0x4FF40000UL)

VSI 4 Base Address

ARM_VSI5_BASE

#define ARM_VSI5_BASE   (0x4FF50000UL)

VSI 5 Base Address

ARM_VSI6_BASE

#define ARM_VSI6_BASE   (0x4FF60000UL)

VSI 6 Base Address

ARM_VSI7_BASE

#define ARM_VSI7_BASE   (0x4FF70000UL)

VSI 7 Base Address

ARM_VSI0

#define ARM_VSI0   ((ARM_VSI_Type *)ARM_VSI0_BASE)

VSI 0 struct

ARM_VSI1

#define ARM_VSI1   ((ARM_VSI_Type *)ARM_VSI1_BASE)

VSI 1 struct

ARM_VSI2

#define ARM_VSI2   ((ARM_VSI_Type *)ARM_VSI2_BASE)

VSI 2 struct

ARM_VSI3

#define ARM_VSI3   ((ARM_VSI_Type *)ARM_VSI3_BASE)

VSI 3 struct

ARM_VSI4

#define ARM_VSI4   ((ARM_VSI_Type *)ARM_VSI4_BASE)

VSI 4 struct

ARM_VSI5

#define ARM_VSI5   ((ARM_VSI_Type *)ARM_VSI5_BASE)

VSI 5 struct

ARM_VSI6

#define ARM_VSI6   ((ARM_VSI_Type *)ARM_VSI6_BASE)

VSI 6 struct

ARM_VSI7

#define ARM_VSI7   ((ARM_VSI_Type *)ARM_VSI7_BASE)

VSI 7 struct